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    ADAPTIVE CLOCK MESH WIRING
    2.
    发明申请
    ADAPTIVE CLOCK MESH WIRING 审中-公开

    公开(公告)号：US20190294203A1

    公开(公告)日：2019-09-26

    申请号：US15925987

    申请日：2018-03-20

    申请人： International Business Machines Corporation

    发明人： Andreas H.A. Arp ,  Fatih Cilek ,  Michael V. Koch ,  Matthias Ringe

    IPC分类号： G06F1/10 ,  G06F1/08

    摘要： Aspects of the present disclosure relate to adaptive mesh wiring. A clock signal is provided to a clock mesh area, wherein the clock mesh area includes a plurality of wires configured in a grid. A pair of loads with impermissible skew within the clock mesh area is identified based on a threshold value. A mesh network area partition enclosing the pair of loads with impermissible skew is determined. Modifications are then made to the mesh network area partition to attempt to reduce skew. In some embodiments, a wire width of a portion of wires included in the mesh network area partition is increased. In some embodiments, a wire is added in between two wires present in the mesh network area partition.

    DYNAMIC CONTROL OF EDGE SHIFT FOR DUTY CYCLE CORRECTION
    3.
    发明申请
    DYNAMIC CONTROL OF EDGE SHIFT FOR DUTY CYCLE CORRECTION 审中-公开

    公开(公告)号：US20190097620A1

    公开(公告)日：2019-03-28

    申请号：US15854985

    申请日：2017-12-27

    申请人： International Business Machines Corporation

    发明人： Andreas H.A. Arp ,  Fatih Cilek ,  Michael V. Koch ,  Matthias Ringe

    IPC分类号： H03K7/08 ,  H03K5/05

    摘要： A duty cycle correction device may be provided for correcting a duty cycle of an input signal. The device includes a first duty cycle correction circuit. The first duty cycle correction circuit receives the input signal. The first duty cycle correction circuit generates a first intermediate signal. The device includes a first programmable delay circuit. The first programmable delay circuit is controlled by a first delay control signal. The first programmable delay circuit receives the first intermediate signal. The first programmable delay circuit generates an output signal. The device includes a second duty cycle correction circuit. The second duty cycle correction circuit receives the input signal. The second duty cycle correction circuit generates a second intermediate signal. The device includes a second programmable delay circuit. The second programmable delay circuit generates a reference signal. The device includes a skew control arrangement operable for generating the first delay control signal.

    YIELD IMPROVING LEAF CELLS OPTIMIZATION FOR SEMICONDUCTOR NETLISTS
    4.
    发明申请
    YIELD IMPROVING LEAF CELLS OPTIMIZATION FOR SEMICONDUCTOR NETLISTS 有权

    公开(公告)号：US20210224462A1

    公开(公告)日：2021-07-22

    申请号：US16747009

    申请日：2020-01-20

    申请人： International Business Machines Corporation

    发明人： Thomas Makowski ,  Matthias Ringe ,  Andreas H.A. Arp ,  Michael V. Koch ,  Fatih Cilek

    IPC分类号： G06F30/398

    摘要： A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.

    ROUTING A CELL OF A SEMICONDUCTOR CHIP
    6.
    发明申请
    ROUTING A CELL OF A SEMICONDUCTOR CHIP 有权

    公开(公告)号：US20210103641A1

    公开(公告)日：2021-04-08

    申请号：US16595957

    申请日：2019-10-08

    申请人： International Business Machines Corporation

    发明人： Thomas Makowski ,  Matthias Ringe ,  Andreas H.A. Arp ,  Michael V. Koch ,  Fatih Cilek

    IPC分类号： G06F17/50

    摘要： Embodiments are disclosed for routing a cell of a semiconductor chip, the cell being represented by a matrix, encoding first tracks of the cell as columns of the matrix and second tracks of the cell as rows of the matrix, respectively. The method includes performing a sweep operation on the matrix, the sweep operation including generating an index structure indexed by columns of the matrix, the index structure including information on candidate cut shapes that can be placed in a particular column of the matrix. Additionally, the method includes recursively placing cut shapes into the cell based on the index structure, one recursion of the placing including finding a possible cut shape and recursively placing the remaining cut shapes.

    CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT
    7.
    发明申请
    CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200169251A1

    公开(公告)日：2020-05-28

    申请号：US16199548

    申请日：2018-11-26

    申请人： International Business Machines Corporation

    发明人： Andreas H.A. Arp ,  Fatih Cilek ,  Michael V. Koch ,  Thomas Makowski ,  Matthias Ringe

    IPC分类号： H03K5/19 ,  H03K5/1534 ,  G01R31/317 ,  G06F1/10

    摘要： An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.