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公开(公告)号：US11275113B2
公开(公告)日：2022-03-15
申请号：US16776803
申请日：2020-01-30
摘要： Measuring a control system response time of a second clock tree is provided, comprising measuring a skew between the second clock signal and the first clock signal and storing the skew, initiating a delay change of a delay induced by the programmable delay line and starting a time measurement. At least one iteration is performed of measuring the skew between the second clock signal and the first clock signal and comparing the measured skew with the stored skew. Based on the result of the comparison, stopping after a current iteration and stopping the time measurement. A result of the time measurement is the control system response time.
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公开(公告)号：US20210224462A1
公开(公告)日：2021-07-22
申请号：US16747009
申请日：2020-01-20
IPC分类号： G06F30/398
摘要： A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.
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公开(公告)号：US10594307B2
公开(公告)日：2020-03-17
申请号：US16174835
申请日：2018-10-30
摘要： A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.
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公开(公告)号：US20190097619A1
公开(公告)日：2019-03-28
申请号：US15855039
申请日：2017-12-27
发明人： Andreas H.A. Arp , Fatih Cilek , Michael V. Koch , Matthias Ringe
CPC分类号： H03K5/1565 , G06F1/04 , G06F1/06 , G06F1/12 , H03K3/017 , H03K5/159 , H03K2005/00254 , H03K2005/00286
摘要： Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.
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公开(公告)号：US11921157B2
公开(公告)日：2024-03-05
申请号：US17467572
申请日：2021-09-07
IPC分类号： G01R31/317 , G01R31/00 , H03K5/00 , H03K5/133 , H03K19/20
CPC分类号： G01R31/31725 , H03K5/133 , G01R31/003 , H03K2005/00078 , H03K2005/0015 , H03K19/20
摘要： A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.
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公开(公告)号：US11176304B2
公开(公告)日：2021-11-16
申请号：US16595957
申请日：2019-10-08
IPC分类号： G06F30/30 , G06F30/394 , G06F119/18
摘要： Embodiments are disclosed for routing a cell of a semiconductor chip, the cell being represented by a matrix, encoding first tracks of the cell as columns of the matrix and second tracks of the cell as rows of the matrix, respectively. The method includes performing a sweep operation on the matrix, the sweep operation including generating an index structure indexed by columns of the matrix, the index structure including information on candidate cut shapes that can be placed in a particular column of the matrix. Additionally, the method includes recursively placing cut shapes into the cell based on the index structure, one recursion of the placing including finding a possible cut shape and recursively placing the remaining cut shapes.
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公开(公告)号：US20210242860A1
公开(公告)日：2021-08-05
申请号：US16776764
申请日：2020-01-30
摘要： A method for cycle accurate deskewing a second clock signal with respect to a first clock signal is provided. The first clock signal has been propagated from a first clock source through a first clock tree. The second clock signal has been propagated from the first clock source through a second clock tree. The second clock tree comprises a programmable delay line for inducing a delay. The method comprises determining a first clock tree latency of the first clock tree, determining a second clock tree latency of the second clock tree, setting a cycle time of the first clock source to a measuring cycle time depending on the first clock tree latency and/or the second clock tree latency, adjusting a skew between the second clock signal and the first clock signal, setting the cycle time of the first clock source to an operating cycle time.
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公开(公告)号：US20190294203A1
公开(公告)日：2019-09-26
申请号：US15925987
申请日：2018-03-20
发明人： Andreas H.A. Arp , Fatih Cilek , Michael V. Koch , Matthias Ringe
摘要： Aspects of the present disclosure relate to adaptive mesh wiring. A clock signal is provided to a clock mesh area, wherein the clock mesh area includes a plurality of wires configured in a grid. A pair of loads with impermissible skew within the clock mesh area is identified based on a threshold value. A mesh network area partition enclosing the pair of loads with impermissible skew is determined. Modifications are then made to the mesh network area partition to attempt to reduce skew. In some embodiments, a wire width of a portion of wires included in the mesh network area partition is increased. In some embodiments, a wire is added in between two wires present in the mesh network area partition.
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公开(公告)号：US10263606B2
公开(公告)日：2019-04-16
申请号：US15792819
申请日：2017-10-25
发明人： Andreas Arp , Fatih Cilek , Michael V. Koch , Matthias Ringe
摘要： A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.
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公开(公告)号：US20190103861A1
公开(公告)日：2019-04-04
申请号：US16174835
申请日：2018-10-30
IPC分类号： H03K5/15
CPC分类号： H03K5/15006 , H03K2005/00058
摘要： A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.
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