公开(公告)号：US20220309000A1

公开(公告)日：2022-09-29

申请号：US17215287

申请日：2021-03-29

申请人： International Business Machines Corporation

发明人： David Campbell ,  George W. Rohrbaugh, III ,  Jake Truelove ,  Jon K. Kriegel ,  Charles D. Wait ,  Jody Joyner

IPC分类号： G06F12/0862 ,  G06F12/0864 ,  G06F12/1045 ,  G06F12/02

摘要： A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.

公开(公告)号：US11734188B2

公开(公告)日：2023-08-22

申请号：US17199315

申请日：2021-03-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Charles D. Wait ,  David Campbell ,  Jake Truelove ,  Jody Joyner ,  Jon K. Kriegel ,  Glenn O. Kincaid

IPC分类号： G06F12/1009 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/1045

CPC分类号： G06F12/1009 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/1054 ,  G06F12/1063

摘要： A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.

公开(公告)号：US11556475B2

公开(公告)日：2023-01-17

申请号：US17215287

申请日：2021-03-29

申请人： International Business Machines Corporation

发明人： David Campbell ,  George W. Rohrbaugh, III ,  Jake Truelove ,  Jon K. Kriegel ,  Charles D. Wait ,  Jody Joyner

IPC分类号： G06F12/0862 ,  G06F12/02 ,  G06F12/1045 ,  G06F12/0864

摘要： A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.

公开(公告)号：US11221957B2

公开(公告)日：2022-01-11

申请号：US16119013

申请日：2018-08-31

申请人： International Business Machines Corporation

发明人： Bartholomew Blaner ,  Jay G. Heaslip ,  Benjamin Herrenschmidt ,  Robert D. Herzl ,  Jody Joyner ,  Jon K. Kriegel ,  Charles D. Wait

IPC分类号： G06F12/0897 ,  G06F12/02 ,  G06F12/1009

摘要： A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

公开(公告)号：US20200073817A1

公开(公告)日：2020-03-05

申请号：US16119013

申请日：2018-08-31

申请人： International Business Machines Corporation

发明人： Bartholomew Blaner ,  Jay G. Heaslip ,  Benjamin Herrenschmidt ,  Robert D. Herzl ,  Jody Joyner ,  Jon K. Kriegel ,  Charles D. Wait

IPC分类号： G06F12/0897 ,  G06F12/02 ,  G06F12/1009

摘要： A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

公开(公告)号：US11636043B2

公开(公告)日：2023-04-25

申请号：US17461919

申请日：2021-08-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Charles D. Wait ,  Jake Truelove ,  David Campbell ,  Jody Joyner ,  Jon K. Kriegel ,  Glenn O. Kincaid

IPC分类号： G06F12/1009

摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

公开(公告)号：US20230062909A1

公开(公告)日：2023-03-02

申请号：US17461919

申请日：2021-08-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Charles D. Wait ,  Jake Truelove ,  David Campbell ,  Jody Joyner ,  Jon K. Kriegel ,  Glenn O. Kincaid

IPC分类号： G06F12/1009

摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

公开(公告)号：US20220292028A1

公开(公告)日：2022-09-15

申请号：US17199315

申请日：2021-03-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Charles D. Wait ,  David Campbell ,  Jake Truelove ,  Jody Joyner ,  Jon K. Kriegel ,  Glenn O. Kincaid

IPC分类号： G06F12/1009 ,  G06F12/1045 ,  G06F12/0864 ,  G06F12/0882

摘要： A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.

公开(公告)号：US10776281B2

公开(公告)日：2020-09-15

申请号：US16152241

申请日：2018-10-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jake Truelove ,  Ronald Kalla ,  Jody Joyner ,  Benjamin Herrenschmidt ,  David A. Larson Stanton

IPC分类号： G06F12/10 ,  G06F12/1045 ,  G06F9/455

摘要： An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.

公开(公告)号：US20200110710A1

公开(公告)日：2020-04-09

申请号：US16152241

申请日：2018-10-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jake Truelove ,  Ronald Kalla ,  Jody Joyner ,  Benjamin HERRENSCHMIDT ,  David A. Larson Stanton

IPC分类号： G06F12/1045 ,  G06F9/455

摘要： An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.