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公开(公告)号：US09342387B1
公开(公告)日：2016-05-17
申请号：US14733227
申请日：2015-06-08
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , John D. Irish , Charles F. Marino , William J. Starke
CPC分类号： G06F9/546
摘要： In a data processing system, a switch of the data processing system receives a request to push a message referenced by an instruction of a sending thread to a receiving thread. In response to receiving the request, the switch determines whether the sending thread is authorized to push the message to the receiving thread by attempting to access an entry of a data structure of the switch utilizing a key derived from at least one identifier of the sending thread. In response to access to the entry being successful, content of the entry is utilized to determine an address of a mailbox of the receiving thread, and the switch pushes the message to the mailbox of the receiving thread. In response to access to the entry not being successful, the switch refrains from pushing the message to the mailbox of the receiving thread.
摘要翻译： 在数据处理系统中，数据处理系统的交换机接收将由发送线程的指令引用的消息推送到接收线程的请求。 响应于接收到请求，交换机通过尝试使用从至少一个发送线程的标识符导出的密钥访问交换机的数据结构的条目来确定发送线程是否被授权将消息推送到接收线程 。 响应对该条目的访问成功，使用该条目的内容来确定接收线程的邮箱的地址，并且交换机将该消息推送到接收线程的邮箱。 响应访问条目不成功，交换机不阻止将消息推送到接收线程的邮箱。
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公开(公告)号：US09286148B1
公开(公告)日：2016-03-15
申请号：US14579614
申请日：2014-12-22
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , John D. Irish , Charles F. Marino , William J. Starke
CPC分类号： G06F9/546
摘要： In a data processing system, a switch of the data processing system receives a request to push a message referenced by an instruction of a sending thread to a receiving thread. In response to receiving the request, the switch determines whether the sending thread is authorized to push the message to the receiving thread by attempting to access an entry of a data structure of the switch utilizing a key derived from at least one identifier of the sending thread. In response to access to the entry being successful, content of the entry is utilized to determine an address of a mailbox of the receiving thread, and the switch pushes the message to the mailbox of the receiving thread. In response to access to the entry not being successful, the switch refrains from pushing the message to the mailbox of the receiving thread.
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公开(公告)号：US09778933B2
公开(公告)日：2017-10-03
申请号：US14733496
申请日：2015-06-08
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Guy L. Guthrie , John D. Irish , William J. Starke , Jeffrey A. Stuecheli
CPC分类号： G06F9/3005 , G06F9/3004 , G06F9/30047 , G06F9/3009 , G06F9/46 , G06F9/546 , G06F13/4022
摘要： In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the first push instruction in a program order. Each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread. In response to executing the first and second push instructions, the processor core transmits respective first and second co-processor requests to a switch in the data processing system via an interconnect fabric of the data processing system. The processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.
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公开(公告)号：US10761995B2
公开(公告)日：2020-09-01
申请号：US16395976
申请日：2019-04-26
发明人： Bartholomew Blaner , Jeffrey A. Stuecheli , Michael S. Siegel , William J. Starke , Curtis C. Wollbrink , Kenneth M. Valk , Lakshminarayana Arimilli , John D. Irish
IPC分类号： G06F12/10 , G06F13/16 , G06F9/38 , G06F12/0817 , G06F12/1027 , G06F12/1045 , G06F3/06 , G06F13/28 , G06F9/455
摘要： An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.
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公开(公告)号：US10528399B2
公开(公告)日：2020-01-07
申请号：US15862705
申请日：2018-01-05
发明人： Mark S. Fredrickson , John Borkenhagen , Michael A. Muston , Spencer K. Millican , John D. Irish
IPC分类号： G06F12/10 , G06F9/50 , G06F12/1045
摘要： Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.
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公开(公告)号：US09766890B2
公开(公告)日：2017-09-19
申请号：US14581202
申请日：2014-12-23
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Guy L. Guthrie , John D. Irish , William J. Starke , Jeffrey A. Stuecheli
CPC分类号： G06F9/3005 , G06F9/3004 , G06F9/30047 , G06F9/3009 , G06F9/46 , G06F9/546 , G06F13/4022
摘要： In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the first push instruction in a program order. Each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread. In response to executing the first and second push instructions, the processor core transmits respective first and second co-processor requests to a switch in the data processing system via an interconnect fabric of the data processing system. The processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.
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7.发明授权公开(公告)号：US09569293B2
公开(公告)日：2017-02-14
申请号：US14733631
申请日：2015-06-08
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Bradly G. Frey , Guy L. Guthrie , John D. Irish , William J. Starke , Jeffrey A. Stuecheli
CPC分类号： G06F9/546 , G06F9/30043 , G06F9/3009 , G06F9/3851 , G06F13/4022 , G06F15/167 , Y02D10/14 , Y02D10/151
摘要： A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.
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8.发明授权公开(公告)号：US11030110B2
公开(公告)日：2021-06-08
申请号：US16395942
申请日：2019-04-26
发明人： Michael S. Siegel , Bartholomew Blaner , Jeffrey A. Stuecheli , William J. Starke , Derek E. Williams , Kenneth M. Valk , John D. Irish , Lakshminarayana Arimilli
IPC分类号： G06F12/10 , G06F13/16 , G06F9/38 , G06F12/0817 , G06F12/1027 , G06F12/1045 , G06F3/06 , G06F13/28 , G06F9/455
摘要： An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.
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公开(公告)号：US20190163633A1
公开(公告)日：2019-05-30
申请号：US15826970
申请日：2017-11-30
IPC分类号： G06F12/0831 , G06F12/0864
摘要： A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.
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公开(公告)号：US09678812B2
公开(公告)日：2017-06-13
申请号：US14579681
申请日：2014-12-22
CPC分类号： G06F9/546 , G06F9/467 , G06F9/4881 , G06F9/54 , G06F9/544
摘要： In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each receive entry includes addressing information for one or more mailboxes into which messages can be injected, a send data structure including send entries each uniquely corresponding to a send window, where each send entry includes a receive window field that identifies one or more receive windows, and switch logic. The switch logic, responsive to a request to push a message to one or more receiving threads, accesses a send entry that corresponds to a send window of the sending thread, utilizes contents of the receive window field of the send entry to access one or more of the receive entries, and pushes the message to one or more mailboxes of one or more receiving threads utilizing the addressing information of the receive entry or entries.
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