公开(公告)号：US10315222B2

公开(公告)日：2019-06-11

申请号：US15294130

申请日：2016-10-14

Applicant: InvenSense, Inc.

Inventor： James Christian Salvia ,  Michael H. Perrott ,  Marian Voros ,  Eldwin Ng ,  Julius Ming-Lin Tsai ,  Nikhil Apte

IPC: B60B1/00 ,  B06B1/06 ,  G06K9/00 ,  G06F3/0354 ,  H01L27/092

Abstract: An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes two semiconductor devices. The plurality of CMOS control elements include a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements including a semiconductor device of a first class and a semiconductor device of a second class, and a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements including a semiconductor device of the first class and a semiconductor device of a third class. The plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.

公开(公告)号：US11440052B2

公开(公告)日：2022-09-13

申请号：US16395045

申请日：2019-04-25

Applicant: InvenSense, Inc.

Inventor： James Christian Salvia ,  Michael H. Perrott ,  Marian Voros ,  Eldwin Ng ,  Julius Ming-Lin Tsai ,  Nikhil Apte

IPC: B06B1/00 ,  B06B1/06 ,  G06F3/0354 ,  G06V40/13 ,  G06V40/12 ,  H01L27/092

Abstract: An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array and a plurality of MEMS devices. Each CMOS control element of the plurality of CMOS control elements includes at least one of a low voltage semiconductor device, a high voltage PMOS semiconductor device, and a high voltage NMOS semiconductor device. Each MEMS device of the plurality of MEMS devices is associated with a CMOS control element of the plurality of CMOS control elements. The plurality of CMOS control elements are arranged in the two-dimensional array such that low voltage semiconductor devices are only adjacent to other low voltage semiconductor devices, high voltage PMOS semiconductor devices are only adjacent to other high voltage PMOS semiconductor devices, and high voltage NMOS semiconductor devices are only adjacent to other high voltage NMOS semiconductor devices.

公开(公告)号：US10656255B2

公开(公告)日：2020-05-19

申请号：US15205743

申请日：2016-07-08

Applicant: InvenSense, Inc.

Inventor： Eldwin Ng ,  Julius Ming-Lin Tsai ,  Nikhil Apte

IPC: H01L41/047 ,  G01S7/521 ,  B06B1/06 ,  H01L41/09 ,  A61B5/1172 ,  A61B8/00 ,  G01S15/89

Abstract: A Piezoelectric Micromachined Ultrasonic Transducer (PMUT) device is provided. The PMUT includes a substrate and an edge support structure connected to the substrate. A membrane is connected to the edge support structure such that a cavity is defined between the membrane and the substrate, where the membrane is configured to allow movement at ultrasonic frequencies. The membrane includes a piezoelectric layer and first and second electrodes coupled to opposing sides of the piezoelectric layer. An interior support structure is disposed within the cavity and connected to the substrate and the membrane.

公开(公告)号：US10325915B2

公开(公告)日：2019-06-18

申请号：US15294186

申请日：2016-10-14

Applicant: InvenSense, Inc.

Inventor： James Christian Salvia ,  Michael H. Perrott ,  Marian Voros ,  Eldwin Ng ,  Julius Ming-Lin Tsai ,  Nikhil Apte

IPC: H01L27/00 ,  H01L27/092 ,  G06K9/00 ,  G06F3/0354 ,  B06B1/06 ,  B81C1/00 ,  H01L21/8238

Abstract: An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes semiconductor devices. The plurality of CMOS control elements each including a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device and an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device. The plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.