公开(公告)号：US10725916B2

公开(公告)日：2020-07-28

申请号：US15612949

申请日：2017-06-02

Applicant: InvenSense, Inc.

Inventor： Vinod Bhat ,  Amr Zaky ,  Jatin Gangani

IPC: G06F12/0815 ,  G01D9/00

Abstract: A system includes sensors, a first memory component, a second memory component, and an interface. The sensors are configured to generate data responsive to stimuli. Each sensor may transmit its associated data as it becomes available. The first memory component may receive and store sensor data. The second memory component may receive data from the first memory component. The interface may receive data from the second memory component. The sensor data generated during a time which the interface is receiving data from the second memory component is transmitted to the first memory component and stored thereto. No data is transmitted from the first memory component or from the sensors to the second memory component during the time which the interface is receiving data from the second memory component. Subsequently, a subset of data stored on the first memory component is advanced to the second memory component.

公开(公告)号：US09235377B2

公开(公告)日：2016-01-12

申请号：US13796997

申请日：2013-03-12

Applicant: Invensense, Inc.

Inventor： Vinod Bhat ,  Behrad Aria

IPC: G06F5/06 ,  G06F12/02 ,  G06F12/06 ,  G06F5/10

CPC classification number: G06F5/10 ,  G06F5/065 ,  G06F12/0223 ,  G06F12/0646 ,  G06F2205/063

Abstract: A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors.

Abstract translation: 设备包括一个或多个传感器，一个或多个处理器，一个或多个传感器和存储器。 存储器具有第一部分，第二部分和第三部分。 第一部分被分配用于存储由一个或多个处理器执行的指令。 分配第二部分以存储由一个或多个处理器生成的数据，并且第三部分被分配用于存储来自一个或多个传感器的数据。 第三部分是具有一个或多个FIFO部分的先进先出（FIFO）。该设备还包括可操作以分配存储器的第一，第二和第三部分的控制逻辑，其中一个或多个FIFO中的每一个 部分被分配给一个或多个传感器中的每一个。 每个FIFO部分的大小取决于传感器的带宽和传感器的数量。

公开(公告)号：US20140281341A1

公开(公告)日：2014-09-18

申请号：US13796997

申请日：2013-03-12

Applicant: INVENSENSE, INC.

Inventor： Vinod Bhat ,  Behrad Aria

IPC: G06F5/14

CPC classification number: G06F5/10 ,  G06F5/065 ,  G06F12/0223 ,  G06F12/0646 ,  G06F2205/063

Abstract: A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors.

Abstract translation: 设备包括一个或多个传感器，一个或多个处理器，一个或多个传感器和存储器。 存储器具有第一部分，第二部分和第三部分。 第一部分被分配用于存储由一个或多个处理器执行的指令。 分配第二部分以存储由一个或多个处理器生成的数据，并且第三部分被分配用于存储来自一个或多个传感器的数据。 第三部分是具有一个或多个FIFO部分的先进先出（FIFO）。该设备还包括可操作以分配存储器的第一，第二和第三部分的控制逻辑，其中一个或多个FIFO中的每一个 部分被分配给一个或多个传感器中的每一个。 每个FIFO部分的大小取决于传感器的带宽和传感器的数量。