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公开(公告)号：US20120219291A1
公开(公告)日：2012-08-30
申请号：US13405530
申请日：2012-02-27
申请人： Isao Chiku , Yukio Suda , Shiuji Sakakura
发明人： Isao Chiku , Yukio Suda , Shiuji Sakakura
IPC分类号： H04J14/00
CPC分类号： H04J3/1652 , H04J3/0691 , H04J2203/0007 , H04J2203/0008
摘要： A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.
摘要翻译： 交叉连接系统包括映射单元，其将与空间开关进行交叉连接的第二信号帧映射到与空间开关进行交叉连接的第三信号帧和时间开关; 选择单元，其选择与空间开关进行交叉连接的第一信号帧和时间切换以及对应的时钟信号，或者选择第三信号帧和对应的时钟信号; 交叉连接单元，其接收由选择单元选择的第一信号帧和相应的时钟信号或第三信号帧和对应的时钟信号，并对第一信号帧或第三信号帧执行交叉连接; 以及解映射单元，将从交叉连接单元输出的第三信号帧解映射成第二信号帧，并输出第二信号帧。
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公开(公告)号：US08780897B2
公开(公告)日：2014-07-15
申请号：US13405530
申请日：2012-02-27
申请人： Isao Chiku , Yukio Suda , Shiuji Sakakura
发明人： Isao Chiku , Yukio Suda , Shiuji Sakakura
IPC分类号： H04L12/50
CPC分类号： H04J3/1652 , H04J3/0691 , H04J2203/0007 , H04J2203/0008
摘要： A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.
摘要翻译： 交叉连接系统包括映射单元，其将与空间开关进行交叉连接的第二信号帧映射到与空间开关进行交叉连接的第三信号帧和时间开关; 选择单元，其选择与空间开关进行交叉连接的第一信号帧和时间切换以及对应的时钟信号，或者选择第三信号帧和对应的时钟信号; 交叉连接单元，其接收由选择单元选择的第一信号帧和相应的时钟信号或第三信号帧和对应的时钟信号，并对第一信号帧或第三信号帧执行交叉连接; 以及解映射单元，将从交叉连接单元输出的第三信号帧解映射成第二信号帧，并输出第二信号帧。
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公开(公告)号：US07978704B2
公开(公告)日：2011-07-12
申请号：US11443243
申请日：2006-05-31
申请人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
发明人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
IPC分类号： H04L12/28
CPC分类号： H04L49/555 , H04L49/30
摘要： In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
摘要翻译： 在帧缓冲器监视方法和装置中，提取关于接收到的帧的信息，并且将添加到帧的开始的监视帧写入FIFO缓冲器。 当从FIFO缓冲器读取监视帧时，根据从读取的监视帧开始的相关信息产生预期信息，将期望信息与监视帧内的帧中包含的帧的信息进行比较 读取，以及期望信息是否与关于帧的信息一致。 作为比较的结果，当确定期望信息与关于帧的信息不一致时，例如， 被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级，或者丢弃该帧。 此外，初始化FIFO缓冲器的写目的地地址和读源地址。
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公开(公告)号：US20070189314A1
公开(公告)日：2007-08-16
申请号：US11443243
申请日：2006-05-31
申请人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
发明人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
IPC分类号： H04L12/56
CPC分类号： H04L49/555 , H04L49/30
摘要： In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
摘要翻译： 在帧缓冲器监视方法和装置中，提取关于接收到的帧的信息，并且将添加到帧的开始的监视帧写入FIFO缓冲器。 当从FIFO缓冲器读取监视帧时，根据从读取的监视帧开始的相关信息产生预期信息，将期望信息与监视帧内的帧中包含的帧的信息进行比较 读取，以及期望信息是否与关于帧的信息一致。 作为比较的结果，当确定期望信息与关于帧的信息不一致时，例如， 被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级，或者丢弃该帧。 此外，初始化FIFO缓冲器的写目的地地址和读源地址。
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公开(公告)号：US06330237B1
公开(公告)日：2001-12-11
申请号：US09150721
申请日：1998-09-10
申请人： Yukio Suda , Satoshi Nemoto , Yasuhiro Murakami , Masahiro Shioda
发明人： Yukio Suda , Satoshi Nemoto , Yasuhiro Murakami , Masahiro Shioda
IPC分类号： H04L1250
CPC分类号： H04L12/43 , H04J2203/0042 , H04J2203/0089 , H04J2203/0091 , H04L2012/5675 , H04Q11/0478
摘要： A time slot assignment circuit capable of performing channel setting with a high efficiency and with a high degree of freedom of channel setting with respect to a large volume of transmission data and in addition having a small circuit scale and low power consumption, provided a time switch provided with a transmission data memory into which transmission data is sequentially written and performing switching in a time domain with respect to the transmission data, a space switch for performing switching in a space domain with respect to an output thereof, an address control memory which outputs a channel setting address for controlling the two switches, and a channel setting information converting unit for converting a channel setting information from the outside to a channel setting address and an accessing address for the memory.
摘要翻译： 一种时隙分配电路，其能够相对于大量的传输数据以高效率和高自由度地进行信道设置，并且另外具有小的电路规模和低功耗，从而提供时间转换 设置有传输数据存储器，传输数据被顺序地写入到传输数据存储器中，并且相对于传输数据在时域中执行切换;空间切换器，用于相对于其输出在空域中执行切换;地址控制存储器，其输出 用于控制两个开关的通道设置地址，以及用于将来自外部的通道设置信息转换为通道设置地址的通道设置信息转换单元和用于存储器的访问地址。
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公开(公告)号：US5627826A
公开(公告)日：1997-05-06
申请号：US444298
申请日：1995-05-18
申请人： Masaru Kameda , Yukio Suda , Toshiaki Ookubo , Hiroshi Yoshida
发明人： Masaru Kameda , Yukio Suda , Toshiaki Ookubo , Hiroshi Yoshida
CPC分类号： H04Q11/06
摘要： A time-slot interchanger includes first and second time switches and a space switch installed between the first and second time switches. The first time switch includes a first part for supplying data, which is produced by adding a blank region to input data supplied to the first time switch, in n systems (n is an integer), in parallel to the space switch. And the second time switch includes a second part for supplying output data, which is produced by removing the blank region from data received in the n systems and in parallel from the space switch.
摘要翻译： 时隙交换器包括第一和第二时间交换机和安装在第一和第二时间交换机之间的空间交换机。 第一时间开关包括与空间开关并行地在n个系统（n为整数）中为提供给第一时间开关的输入数据添加空白区域而提供数据的第一部分。 并且第二时间切换器包括用于提供输出数据的第二部分，其通过从在n个系统中接收的并从空间交换机接收的数据中去除空白区域而产生。
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公开(公告)号：US07463169B2
公开(公告)日：2008-12-09
申请号：US11877831
申请日：2007-10-24
申请人： Masayuki Horie , Yukio Suda
发明人： Masayuki Horie , Yukio Suda
IPC分类号： H03M7/00
CPC分类号： H03M7/04
摘要： In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.
摘要翻译： 在用于64B / 66B编码的更有效的数据生成方法和电路中，当分组数据和数据分组的头尾信息被接收时，写入将头尾识别字节分别添加到头部的用户数据， 基于头尾信息的分组数据的尾部与从存储器的预定地址顺序地指示要写入存储器的两个识别字节的位置的控制数据相关联。 从预定地址，按8字节的用户数据和对应于用户数据的控制数据被顺序读取以提供给64B / 66B编码电路。 在不能进行读取的期间，8n字节（n> = 1）的空闲字节和指示空闲字节的控制数据，或8n字节（n> = 2）的维护用户数据，其中头和尾 识别字节分别被添加到维护信息的头部和尾部，并且指示两个标识字节的位置的控制数据被提供给64B / 66B编码电路。
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公开(公告)号：US20080100481A1
公开(公告)日：2008-05-01
申请号：US11877831
申请日：2007-10-24
申请人： Masayuki Horie , Yukio Suda
发明人： Masayuki Horie , Yukio Suda
IPC分类号： H03M5/00
CPC分类号： H03M7/04
摘要： In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.
摘要翻译： 在用于64B / 66B编码的更有效的数据生成方法和电路中，当分组数据和数据分组的头尾信息被接收时，写入将头尾识别字节分别添加到头部的用户数据， 基于头尾信息的分组数据的尾部与从存储器的预定地址顺序地指示要写入存储器的两个识别字节的位置的控制数据相关联。 从预定地址，按8字节的用户数据和对应于用户数据的控制数据被顺序读取以提供给64B / 66B编码电路。 在不能进行读取的期间，8n字节（n> = 1）的空闲字节和指示空闲字节的控制数据，或8n字节（n> = 2）的维护用户数据，其中头和尾 识别字节分别被添加到维护信息的头部和尾部，并且指示两个标识字节的位置的控制数据被提供给64B / 66B编码电路。
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公开(公告)号：US5014271A
公开(公告)日：1991-05-07
申请号：US323944
申请日：1989-03-15
申请人： Naonobu Fujimoto , Yukio Suda , Katsutoshi Miyaji
发明人： Naonobu Fujimoto , Yukio Suda , Katsutoshi Miyaji
CPC分类号： H04J3/076
摘要： A pulse insertion circuit alternately distributes serial input data at a predetermined data clocking rate into first and second parallel input data, which are synchronously and simultaneously written into and read from a memory, the second input data as read being delayed by one bit. A selection means selects between the second input data and the one-bit delayed second input data and further switches between and establishes either a direct or a cross connection between the selected one of the second input data, as read or as delayed, and the first input data and the first and second output terminals thereof, at which there are produced, correspondingly, parallel and selected, first and second input data. A control means responds to a pulse insertion request to inhibit memory read-out by one read clock period and to control the switching means selectively to switch between the direct and cross-connections, the pulse addition being made to one of the parallel and selected, first and second input data, as specified by the pulse insertion request. Pulse insertion thus is performed at one-half the predetermined clocking rate, the selected and parallel, first and second input data with the required pulse inserted in the specified one thereof, thereafter being multiplexed and transmitted at the predetermined clocking rate.
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公开(公告)号：US08730792B2
公开(公告)日：2014-05-20
申请号：US13036227
申请日：2011-02-28
申请人： Satoshi Nemoto , Yukio Suda
发明人： Satoshi Nemoto , Yukio Suda
IPC分类号： G01R31/08
CPC分类号： H04L49/505 , H04L47/11 , H04L47/283 , H04L49/1515
摘要： Each of a first switching processor and a second switching processor included in a switching device switches plural pieces of data to determined destinations. A controller bypass-transmits a determined number of pieces of data received by the first switching processor to the second switching processor according to a congestion state of the first switching processor to make both of the first switching processor and the second switching processor perform a switching process. Alternatively, the controller bypass-transmits a determined number of pieces of data received by the second switching processor to the first switching processor according to a congestion state of the second switching processor to make both of the first switching processor and the second switching processor perform a switching process.
摘要翻译： 包括在切换装置中的第一切换处理器和第二切换处理器各自将多条数据切换到确定的目的地。 控制器根据第一交换处理器的拥塞状态旁路 - 将由第一交换处理器接收的确定数量的数据发送到第二交换处理器，以使第一交换处理器和第二交换处理器都执行切换处理 。 或者，控制器根据第二交换处理器的拥塞状态，将由第二交换处理器接收的确定数量的数据发送到第一交换处理器，以使第一交换处理器和第二交换处理器都执行 切换过程。
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