公开(公告)号：US5014271A

公开(公告)日：1991-05-07

申请号：US323944

申请日：1989-03-15

申请人： Naonobu Fujimoto ,  Yukio Suda ,  Katsutoshi Miyaji

发明人： Naonobu Fujimoto ,  Yukio Suda ,  Katsutoshi Miyaji

IPC分类号： H04J3/06 ,  H04J3/07

CPC分类号： H04J3/076

摘要： A pulse insertion circuit alternately distributes serial input data at a predetermined data clocking rate into first and second parallel input data, which are synchronously and simultaneously written into and read from a memory, the second input data as read being delayed by one bit. A selection means selects between the second input data and the one-bit delayed second input data and further switches between and establishes either a direct or a cross connection between the selected one of the second input data, as read or as delayed, and the first input data and the first and second output terminals thereof, at which there are produced, correspondingly, parallel and selected, first and second input data. A control means responds to a pulse insertion request to inhibit memory read-out by one read clock period and to control the switching means selectively to switch between the direct and cross-connections, the pulse addition being made to one of the parallel and selected, first and second input data, as specified by the pulse insertion request. Pulse insertion thus is performed at one-half the predetermined clocking rate, the selected and parallel, first and second input data with the required pulse inserted in the specified one thereof, thereafter being multiplexed and transmitted at the predetermined clocking rate.

公开(公告)号：US5327275A

公开(公告)日：1994-07-05

申请号：US784211

申请日：1991-10-30

申请人： Kazuo Yamane ,  Naonobu Fujimoto ,  Takashi Kihara ,  Takeo Fukushima ,  Koichi Nishimura ,  Hatsumi Iino

发明人： Kazuo Yamane ,  Naonobu Fujimoto ,  Takashi Kihara ,  Takeo Fukushima ,  Koichi Nishimura ,  Hatsumi Iino

IPC分类号： H04B10/032 ,  H04B10/08 ,  H04J14/00

CPC分类号： H04J14/0295 ,  H04B10/032 ,  H04J14/0291 ,  H04J14/0279

摘要： A system for optical communication between first and second optical terminal stations, containing a plurality of working optical transmission lines each for connecting between the first and second optical terminal stations, a protection optical transmission line. Each of the first and second optical terminal stations contains a plurality of working pieces of optical terminal equipment, connected to the respective working optical transmission lines, a protection piece of optical terminal equipment connected to the protection optical transmission line, and a plurality of bidirectional optical signal paths, provided corresponding to the respective working pieces of optical terminal equipment, and each operative to connect the corresponding working piece of optical terminal equipment to the protection piece of optical terminal equipment.

摘要翻译： 一种用于在第一和第二光学终端站之间进行光通信的系统，包括用于在第一和第二光学终端站之间连接的多条工作光传输线路，保护光传输线路。 第一和第二光学终端站中的每一个包含连接到各个工作光传输线的多个光终端设备的工作件，连接到保护光传输线的光终端设备的保护片，以及​​多个双向光 信号路径，其对应于光学终端设备的各个工作件，并且各自操作以将光学终端设备的相应工作件连接到光学终端设备的保护件。

公开(公告)号：US4748623A

公开(公告)日：1988-05-31

申请号：US60488

申请日：1987-06-11

申请人： Naonobu Fujimoto

发明人： Naonobu Fujimoto

IPC分类号： H04J3/06 ,  H04L7/08 ,  H04L1/02

CPC分类号： H04J3/0605

摘要： A frame synchronizing circuit uses parallel processing of a received multiplexed signal to detect frame synchronization. The input signal is separated into a predetermined number of signal trains. A matching number of frame synchronizing pattern detection circuits detect the presence of the frame synchronizing pattern by each of the frame synchronizing pattern detection circuits detecting the presence of a modified frame synchronizing pattern. The modified frame synchronizing patterns all contain the same sequence of bits, but the leading bit of the frame synchronizing pattern is in a different signal train in each of the modified frame synchronizing patterns. Timing comparison circuits corresponding to the modified frame synchronizing pattern detection circuits indicate which, if any, of the modified frame synchronizing patterns, are in coincidence with a frame pulse generated at the time the frame synchronizing pattern is expected to be detected. Synchronization guarding circuits corresponding to the timing comparison circuits indicate which, if any, of the modified frame synchronizing patterns is in synchronization with the frame pulse. A timing control circuit adjusts the timing of the frame pulse when the timing comparsion and synchronization guarding circuits indicate noncoincidence and asynchronization of all of the modified frame synchronizing patterns.

摘要翻译： 帧同步电路使用接收的复用信号的并行处理来检测帧同步。 输入信号被分成预定数量的信号列。 匹配数量的帧同步模式检测电路通过检测修改的帧同步模式的存在的每个帧同步模式检测电路检测帧同步模式的存在。 修改的帧同步模式全部包含相同的比特序列，但是帧同步模式的前导比特在每个修改的帧同步模式中处于不同的信号队列中。 对应于修改的帧同步模式检测电路的定时比较电路指示修改的帧同步模式中的哪一个（如果有的话）与期望帧同步模式被检测时产生的帧脉冲一致。 对应于定时比较电路的同步保护电路指示哪个修改的帧同步模式与帧脉冲同步。 当定时比较和同步保护电路指示所有修改的帧同步模式的不一致和不同步时，定时控制电路调整帧脉冲的定时。

公开(公告)号：US5406255A

公开(公告)日：1995-04-11

申请号：US967692

申请日：1992-10-27

申请人： Naonobu Fujimoto ,  Sakutaro Sato

发明人： Naonobu Fujimoto ,  Sakutaro Sato

IPC分类号： H04B1/74 ,  G08B26/00 ,  G08B19/00

CPC分类号： G08B26/00

摘要： A communication system comprising at least one working system for receiving a signal from a source, at least one protection system for receiving the signal from the source, a detection part for detecting an alarm state of the signals received via the working system and the protection system and for outputting an alarm signal if the alarm state is detected in at least one of the working system and the protection system, a switching part for selectively outputting the signal received via one of the working system and the protection system in response to a control signal which determines a connection of the switching part, and a control part for supplying the control signal to the switching part based on the alarm signals from the detection part. The control part disregards the alarm signals if the alarm signals are generated from the detection part with respect to the working system and the protection signal approximately at the same time.

摘要翻译： 一种通信系统，包括用于从源接收信号的至少一个工作系统，用于从源接收信号的至少一个保护系统，用于检测经由工作系统接收的信号的报警状态的检测部分和保护系统 并且如果在所述工作系统和所述保护系统中的至少一个中检测到所述报警状态，则输出报警信号;切换部，用于响应于控制信号有选择地输出经由所述工作系统和所述保护系统之一接收的信号 确定开关部分的连接;以及控制部分，用于根据来自检测部分的报警信号向开关部件提供控制信号。 如果相对于工作系统从检测部分产生报警信号，并且大致同时地产生保护信号，则控制部分忽略报警信号。

公开(公告)号：US4754456A

公开(公告)日：1988-06-28

申请号：US945671

申请日：1986-11-20

申请人： Yoshiaki Yato ,  Takeo Fukushima ,  Naonobu Fujimoto

发明人： Yoshiaki Yato ,  Takeo Fukushima ,  Naonobu Fujimoto

IPC分类号： H04J3/06 ,  H04J3/04 ,  H04J3/14 ,  H04J3/02

CPC分类号： H04J3/14

摘要： A Multiplex system for further multiplexing signals output by low group multiplexers by means of a high group multiplexer. In this system, when at least one of the low group multiplexers is in a fault state, an alternating pattern signal is supplied to the high group multiplexer instead of the signal output by the faulty low group multiplexer, whereby the ratio of "0" and "1" of the signal output by the high group multiplexer becomes almost 1:1.

摘要翻译： PCT No.PCT / JP86 / 00148 Sec。 371日期：1986年11月20日 102（e）1986年11月20日日期PCT提交1986年3月27日PCT公布。 出版物WO86 / 05939 日期1986年10月9日。一种用于通过高组多路复用器进一步复用由低组多路复用器输出的信号的多路复用系统。 在该系统中，当低组多路复用器中的至少一个处于故障状态时，交替模式信号被提供给高组多路复用器而不是故障低组多路复用器输出的信号，由此比率“0”和 由高组多路复用器输出的信号的“1”变为几乎1：1。

公开(公告)号：US4885746A

公开(公告)日：1989-12-05

申请号：US728191

申请日：1985-04-29

申请人： Takeo Fukushima ,  Masami Mizuguchi ,  Takahiro Furukawa ,  Yoshiaki Yato ,  Kenji Sato ,  Naonobu Fujimoto ,  Tetsuro Murase

发明人： Takeo Fukushima ,  Masami Mizuguchi ,  Takahiro Furukawa ,  Yoshiaki Yato ,  Kenji Sato ,  Naonobu Fujimoto ,  Tetsuro Murase

IPC分类号： H04J3/07

CPC分类号： H04J3/07

摘要： A stuff (or dummy) pulse and a stuff designation pulse which indicates existence of nonexistence of the dummy pulse are inserted in a multiplexed pulse code modulation signal to convert an input signal frequency to a higher frequency. The frame synchronization pulse is used as the stuff designation pulse. Therefore, stuff designation is possible even when the frequency difference between the input signal frequency and output signal frequency is small.

摘要翻译： 指示存在虚拟脉冲的存在的填充（或虚拟）脉冲和填充指定脉冲被插入到复用的脉冲编码调制信号中，以将输入信号频率转换为更高的频率。 帧同步脉冲用作填充指定脉冲。 因此，即使输入信号频率和输出信号频率之间的频率差小，也可以进行填充指定。

公开(公告)号：US4727541A

公开(公告)日：1988-02-23

申请号：US804550

申请日：1985-12-04

申请人： Masakazu Mori ,  Takeo Fukushima ,  Naonobu Fujimoto

发明人： Masakazu Mori ,  Takeo Fukushima ,  Naonobu Fujimoto

IPC分类号： H04J3/06 ,  H04J3/04 ,  H04L5/22

CPC分类号： H04L5/22 ,  H04J3/047

摘要： A hierarchical data transmission system is comprised, on the transmitter side, of pre-group multiplexers and a main-group multiplexer and, on the receiver side, of a main-group demultiplexer and pre-group demultiplexers. The main-group multiplexer is fabricated as a parallel-serial converting unit, and the main-group demultiplexer is fabricated as a serial-parallel converting unit. Each of the pre-group multiplexers produces a pre-group data train having a sub-data signal which is also utilized for distinguishing one pre-group data train from another. Each of the pre-group demultiplexers is provided with a discriminator operative, by using the sub-data signal, to distinguish one received pre-group data train from another.

摘要翻译： 分组数据传输系统在发射机侧包括组前多路复用器和主组多路复用器，并且在接收机侧包括主组解复用器和组前解复用器。 主组多路复用器被制造为并行串行转换单元，并且主组解复用器被制造为串行 - 并行转换单元。 每个前置组多路复用器产生具有子数据信号的预组数据序列，该子数据信号也用于区分一组预组数据串与另一组。 每个组前解复用器都具有鉴别器，通过使用子数据信号来区分一个接收到的组前数据序列与另一个。

公开(公告)号：US5737373A

公开(公告)日：1998-04-07

申请号：US321413

申请日：1994-10-11

申请人： Sakutaro Sato ,  Naonobu Fujimoto

发明人： Sakutaro Sato ,  Naonobu Fujimoto

IPC分类号： H03L7/08 ,  H03L7/081 ,  H03L7/14 ,  H03L7/18 ,  H04B10/00 ,  H04B10/07 ,  H04B10/2507 ,  H04J3/00 ,  H04J3/07 ,  H04L7/033 ,  H03L7/00 ,  H04L29/00

CPC分类号： H03L7/18 ,  H03L7/08 ,  H03L7/081 ,  H04J3/076

摘要： Provision is made of a phase-locked loop circuit including a voltage-controlled oscillator, a phase comparator, and a low-pass filter, a pulse-cancelling processing unit, a pulse-cancelling control unit, and a divider circuit. By dividing the pulse-cancelling request signal of the pointer-action into several bits by the divider circuit, the pulse-cancelling control unit gradually changes the input phase to the phase comparator or the control voltage to the voltage-controlled oscillator in several stages from the state before the 1-bit pulse-cancelling to the state of the 1-bit pulse-cancelling so that the phase of the output clock signal from the voltage-controlled oscillator matches the 1-bit pulse-cancelled input clock signal. By this, phase control of the output clock signal is performed in units of less than 1-bit and jitter is suppressed.

摘要翻译： 提供包括压控振荡器，相位比较器和低通滤波器的锁相环电路，脉冲消除处理单元，脉冲消除控制单元和分频器电路。 通过除法器电路将指针动作的脉冲消除请求信号除以若干位，脉冲消除控制单元从多个阶段逐渐将输入相位改变为相位比较器或压控振荡器的控制电压 1位脉冲消除之前的状态到1位脉冲消除的状态，使得来自压控振荡器的输出时钟信号的相位与1位脉冲消除的输入时钟信号匹配。 由此，以小于1位为单位进行输出时钟信号的相位控制，抑制抖动。

公开(公告)号：US5134609A

公开(公告)日：1992-07-28

申请号：US474103

申请日：1990-04-26

申请人： Masakazu Mori ,  Masanori Arai ,  Kazuo Takatsu ,  Naonobu Fujimoto ,  Nobuhide Yamaguchi

发明人： Masakazu Mori ,  Masanori Arai ,  Kazuo Takatsu ,  Naonobu Fujimoto ,  Nobuhide Yamaguchi

IPC分类号： H04J3/08

CPC分类号： H04J3/08

摘要： A drop/insert selecting system for an optical transmission system has a decreased circuit scale, by providing a switching unit (4,4') having a plurality of input terminals for receiving a plurality of input channels and a plurality of output terminals, each of the input channels conveying a frame synchronization signal and a channel number. At at least one drop/insert unit (51,52,51',52') is provided for sequentially generating channel preselection signals until a frame synchronization is established and for dropping or inserting necessary signals from or into a corresponding one of the necessary channels incorporated into the drop/insert units when a frame synchronization is established. A channel selecting unit (6,6a,6b) is provided for generating a plurality of channel selecting signals in response to each of the channel preselection signals, each of the channel selecting signals functioning to connect each of the output terminals to one of the plurality of input terminals. The remaining output terminals of the switching unit are connected to through-channels to which no drop/insert units are connected.

摘要翻译： PCT No.PCT / JP89 / 00870 Sec。 371日期：1990年04月26日 102（e）日期1990年4月26日PCT提交1989年8月25日PCT公布。 公开号WO90 / 02454 日期：1990年3月8日。通过提供具有多个用于接收多个输入通道的输入端子的开关单元（4,4'），用于光传输系统的放置/插入选择系统具有减小的电路规模，以及 多个输出端子，每个输入通道传送帧同步信号和通道号。 在至少一个插入/插入单元（51,52,51'，52'）被提供用于顺序地产生信道预选信号，直到建立帧同步并且用于从必需信道中的相应一个信道中丢弃或插入必要的信号 当建立帧同步时，将其合并到丢弃/插入单元中。 提供频道选择单元（6,6a，6b），用于响应于每个频道预选信号而产生多个频道选择信号，每个频道选择信号用于将每个输出终端连接到多个频道选择单元 的输入端子。 开关单元的其余输出端子连接到没有连接到插座单元的通道。

公开(公告)号：US4811341A

公开(公告)日：1989-03-07

申请号：US1032

申请日：1987-01-07

申请人： Naonobu Fujimoto ,  Takashi Yorita ,  Yoshiaki Yato ,  Yoshinori Nakamura ,  Kenji Satoh

发明人： Naonobu Fujimoto ,  Takashi Yorita ,  Yoshiaki Yato ,  Yoshinori Nakamura ,  Kenji Satoh

IPC分类号： H04L7/04 ,  H04J3/00 ,  H04J3/04 ,  H04J3/06 ,  H04J3/02

CPC分类号： H04J3/047

摘要： A hierarchical data transmission system outputs a high speed second data train by step-by-step multiplexing a plurality of first data trains. A first signal processing part operates at the processing speed corresponding to the first data train, a third signal processing part operates at the processing speed corresponding to the second data train, and a second signal processing part operates at the processing speed corresponding to the intermediate speed of the first data train and second data train. A first clock signal of the speed corresponding to the processing speed of the third signal processing part, a second clock signal of the speed corresponding to the processing speed of the second signal processing part by dividing the first clock signal, and a third clock signal of the speed corresponding to the processing speed of the third signal processing part are generated the first signal processing part operates in association with the third signal processing part, by dividing the second clock signal after the phase adjustment with reference to the phase information of the first clock signal.

摘要翻译： 分级数据传输系统通过逐步复用多个第一数据列输出高速第二数据序列。 第一信号处理部以与第一数据串对应的处理速度进行动作，第三信号处理部以与第二数据串对应的处理速度进行动作，第二信号处理部以对应于中间速度的处理速度 的第一数据列和第二数据列。 对应于第三信号处理部分的处理速度的速度的第一时钟信号，对应于第二信号处理部分的处理速度的速度的第二时钟信号通过划分第一时钟信号，以及第三时钟信号 产生与第三信号处理部分的处理速度相对应的速度，第一信号处理部分与第三信号处理部分相关联地操作，通过参考相位调整之后的第二时钟信号参考第一时钟的相位信息 信号。