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公开(公告)号：US10111189B2
公开(公告)日：2018-10-23
申请号：US14860181
申请日：2015-09-21
IPC分类号： H04W56/00
摘要： In one embodiment, a timing slave packet switching device receives a received primary reference clock signal. The timing slave packet switching device communicates a first plurality of packet network synchronization packets over a packet switching network with a remote primary reference clock source and derives an over-network clock based on the first plurality of packet network synchronization packets. A phase offset between the phase of the over-network clock and the phase of the received primary reference clock signal is determined and typically stored in non-volatile storage. Subsequent to said determining the phase offset, the timing slave packet switching device communicates a second plurality of packet network synchronization packets over the packet switching network with the remote primary reference clock source and adjusts the phase of a clock derived from the second plurality of packet network synchronization packets based on the phase offset.
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2.发明申请Enhanced Phase Synchronization of a Timing Slave Apparatus in a Packet Switching Network 审中-公开分组交换网络中的定时从设备的增强的相位同步公开(公告)号：US20170034797A1
公开(公告)日：2017-02-02
申请号：US14860181
申请日：2015-09-21
IPC分类号： H04W56/00
CPC分类号： H04W56/001
摘要： In one embodiment, a timing slave packet switching device receives a received primary reference clock signal. The timing slave packet switching device communicates a first plurality of packet network synchronization packets over a packet switching network with a remote primary reference clock source and derives an over-network clock based on the first plurality of packet network synchronization packets. A phase offset between the phase of the over-network clock and the phase of the received primary reference clock signal is determined and typically stored in non-volatile storage. Subsequent to said determining the phase offset, the timing slave packet switching device communicates a second plurality of packet network synchronization packets over the packet switching network with the remote primary reference clock source and adjusts the phase of a clock derived from the second plurality of packet network synchronization packets based on the phase offset.
摘要翻译： 在一个实施例中，定时从分组交换设备接收接收的主参考时钟信号。 定时从分组交换设备通过分组交换网络与远程主参考时钟源通信第一多个分组网络同步分组，并且基于第一多个分组网络同步分组导出超网络时钟。 确定过网络时钟的相位与接收的主参考时钟信号的相位之间的相位偏移，并且通常将其存储在非易失性存储器中。 在所述确定相位偏移之后，定时从分组交换设备通过分组交换网络与远程主参考时钟源通信第二多个分组网络同步分组，并且调整从第二多个分组网络导出的时钟的相位 基于相位偏移的同步数据包。
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3.发明授权On-chip testing of embedded memories using Address Space Identifier bus in SPARC architectures 有权在SPARC架构中使用地址空间标识符总线对嵌入式存储器进行片上测试公开(公告)号：US07127640B2
公开(公告)日：2006-10-24
申请号：US10611467
申请日：2003-06-30
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602
摘要： A system for on-chip testing of embedded memories using Address Space Identifier (ASI) bus in Scalable Processor ARChitecture (SPARC) microprocessors. An integrated circuit includes a plurality of memory arrays, Address Space Identifier (ASI) bus interface logic connected by an ASI bus to the plurality of memory arrays, and a memory control unit and a memory built-in self-test (MBIST) engine connected to the ASI bus interface logic. Rather than direct access, the MBIST engine utilizes the ASI bus interface logic and the ASI bus to perform memory testing. The MBIST engine, programmed with memory array parameters, includes a programmable state machine controller to which is connected a programmable data generator, a programmable address generator, and a programmable comparator. The data generator provides data as appropriate. The address generator provides addresses as appropriate. The comparator provides test results information for the particular test situation. The MBIST engine generates a test status output.
摘要翻译： 在可扩展处理器ARChitecture（SPARC）微处理器中使用地址空间标识符（ASI）总线对嵌入式存储器进行片上测试的系统。 集成电路包括多个存储器阵列，通过ASI总线连接到多个存储器阵列的地址空间标识符（ASI）总线接口逻辑，以及连接到存储器控制单元和存储器内置自检（MBIST）引擎 到ASI总线接口逻辑。 MBIST引擎不是直接访问，而是使用ASI总线接口逻辑和ASI总线进行内存测试。 使用存储器阵列参数编程的MBIST引擎包括可编程状态机控制器，其连接有可编程数据发生器，可编程地址发生器和可编程比较器。 数据发生器根据需要提供数据。 地址生成器根据需要提供地址。 比较器提供特定测试情况的测试结果信息。 MBIST引擎生成测试状态输出。
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4.发明授权Method for operating a boundary scan cell design for high performance I/O cells 有权用于操作高性能I / O单元的边界扫描单元设计的方法公开(公告)号：US06578168B1
公开(公告)日：2003-06-10
申请号：US09616825
申请日：2000-07-14
IPC分类号： G01R3128
CPC分类号： G06F11/267 , G01R31/318536 , G01R31/318541 , G01R31/318552
摘要： A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.
摘要翻译： 一种边界扫描单元设计，其将多路复用器放置在功能线路上的功能翻转之前，减少了关键路径中的多路复用器延迟。 这优化了多路复用器和功能触发器方向，从而显着减少了从功能触发器输出到引脚或CPU内部（时钟到q延迟）所需的时间。 为了确保边界扫描模式正常工作，当边界扫描单元处于边界扫描模式时，功能触发器可被设计为充当缓冲器，即变得透明。
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公开(公告)号：US06567944B1
公开(公告)日：2003-05-20
申请号：US09616826
申请日：2000-07-14
IPC分类号： G01R3128
CPC分类号： G01R31/318536 , G01R31/318541 , G01R31/318552 , G06F11/27
摘要： A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.
摘要翻译： 一种边界扫描单元设计，其将多路复用器放置在功能线路上的功能翻转之前，减少了关键路径中的多路复用器延迟。 这优化了多路复用器和功能触发器方向，从而显着减少了从功能触发器输出到引脚或CPU内部（时钟到q延迟）所需的时间。 为了确保边界扫描模式正常工作，当边界扫描单元处于边界扫描模式时，功能触发器可被设计为充当缓冲器，即变得透明。
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公开(公告)号：US07890826B2
公开(公告)日：2011-02-15
申请号：US11636748
申请日：2006-12-11
CPC分类号： G01R31/318544 , G01R31/318594
摘要： A method and apparatus for test of asynchronous pipelines. An asynchronous data pipeline includes first and second pluralities of pipeline stages in an alternating sequence. Each of the pipeline stages includes a control circuit, a latch circuit configured to latch data responsive to an indication from the control circuit, and a combinational logic circuit coupled to receive data from an output of the latch circuit. Each of the latch circuits is scannable. The latch circuits of the first and second pluralities of pipeline stages form a data scan chain configured to load test data into the combinational logic circuits during testing of the data pipeline. The data pipeline further includes a control scan chain configured to load control data for operating the control circuits during testing of the data pipeline. Testing of the data pipeline can include independent testing of the control portion or the data portion.
摘要翻译： 一种用于异步管道测试的方法和装置。 异步数据流水线包括交替序列中的第一和第二多个流水线级。 每个流水线级包括控制电路，锁存电路，被配置为响应于来自控制电路的指示来锁存数据;以及组合逻辑电路，被耦合以从锁存电路的输出接收数据。 每个锁存电路都是可扫描的。 第一和第二多个流水线级的锁存电路形成数据扫描链，其配置为在测试数据管线期间将测试数据加载到组合逻辑电路中。 数据流水线还包括控制扫描链，其被配置为在测试数据流水线期间加载用于操作控制电路的控制数据。 数据管线的测试可以包括控制部分或数据部分的独立测试。
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公开(公告)号：US07779316B2
公开(公告)日：2010-08-17
申请号：US11950578
申请日：2007-12-05
IPC分类号： G11C29/00
CPC分类号： G06F11/267 , G01R31/318533
摘要： A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.
摘要翻译： 用于以功能（操作）速度测试芯片的方法和系统。 芯片可以包括具有布置成逻辑功能元件的数字触发器和存储器阵列的集成电路。 可以包括额外的触发器以输出到一个或多个其他触发器，以便以功能速度向触发器提供输入，使得接收触发器在下一个功能时钟脉冲下根据所接收的输入以功能速度执行，以便于 以功能速度测试芯片。
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8.发明授权公开(公告)号：US07657804B2
公开(公告)日：2010-02-02
申请号：US11582803
申请日：2006-10-18
申请人： Ishwardutt Parulkar
发明人： Ishwardutt Parulkar
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31726 , G01R31/31937
摘要： A method and apparatus for conveying test response data from an integrated circuit to ATE via a plesiochronous interconnect. The integrated circuit includes a core logic unit and a first transmitter coupled thereto by a first data path. In a normal mode, data conveyed from the core logic unit to the transmitter may be transmitted plesiochronously over an interconnect coupled to the transmitter output. The integrated circuit further includes a second data path coupled between the core logic unit and the interconnect. During a test mode, test response data may be conveyed from the core logic unit to ATE via the second data path and the interconnect, wherein the test response data is synchronously transmitted over the interconnect.
摘要翻译： 一种用于将测试响应数据从集成电路经由精密同步互连传送到ATE的方法和装置。 集成电路包括核心逻辑单元和通过第一数据路径耦合到其的第一发射器。 在正常模式中，从核心逻辑单元传输到发射机的数据可以通过耦合到发射机输出的互连网络进行多个传输。 集成电路还包括耦合在核心逻辑单元和互连之间的第二数据路径。 在测试模式期间，测试响应数据可以经由第二数据路径和互连从核心逻辑单元传送到ATE，其中测试响应数据通过互连同步传输。
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公开(公告)号：US20090150112A1
公开(公告)日：2009-06-11
申请号：US11950782
申请日：2007-12-05
申请人： Ishwardutt Parulkar
发明人： Ishwardutt Parulkar
IPC分类号： G01R31/28
CPC分类号： G01R31/318558
摘要： A method of testing chips for manufacturing defects or operational based defects. The method may be used with any chip having logically function elements, including chips having multiple cores configured to be physically and logically identical. The method may be used to limit the total number of bits required to test the cores by demultiplexing and/or compacting the bits provided to the cores and/or outputted from the cores during a scan test.
摘要翻译： 测试用于制造缺陷或基于操作的缺陷的芯片的方法。 该方法可以与具有逻辑功能元件的任何芯片一起使用，包括具有被配置为在物理上和逻辑上相同的多个核的芯片。 该方法可以用于通过在扫描测试期间通过解复用和/或压缩提供给核心和/或从核心输出的比特来限制测试核心所需的总位数。
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10.发明申请公开(公告)号：US20090125770A1
公开(公告)日：2009-05-14
申请号：US11940043
申请日：2007-11-14
申请人： Ishwardutt Parulkar
发明人： Ishwardutt Parulkar
CPC分类号： G01R31/318533
摘要： A method and circuit for capturing and observing the internal state of an integrated circuit that utilizes a scan chain capable of capturing the functional state of an integrated circuit during functional testing without interrupting the functional testing. The functional state may be captured by and shifted out of the scan chain concurrently with functional testing. The scan chain includes sequential elements, each having a functional state and a scan state that operate in parallel. The method and circuit may further include a signature analyzer for compressing the contents of the scan chain into a signature. The method and circuit may capture and compress multiple functional states into a combined signature.
摘要翻译： 一种用于捕获和观察集成电路的内部状态的方法和电路，其利用能够在功能测试期间捕获集成电路的功能状态的扫描链，而不中断功能测试。 功能状态可以与功能测试同时捕获并从扫描链中移出。 扫描链包括顺序元件，每个元件具有并行操作的功能状态和扫描状态。 该方法和电路还可以包括用于将扫描链的内容压缩成签名的签名分析器。 该方法和电路可以将多个功能状态捕获并压缩成组合签名。
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