公开(公告)号：US5787041A

公开(公告)日：1998-07-28

申请号：US724204

申请日：1996-10-01

申请人： J. Michael Hill ,  Donald R. Weiss

发明人： J. Michael Hill ,  Donald R. Weiss

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/00 ,  G11C7/1042

摘要： An improved random access memory (RAM) system enhances the speed and reduces power dissipation and logic complexity associated with a RAM. The RAM system includes first and second pluralities of RAM cell columns. Each of the columns includes (1) at least one RAM cell, each RAM cell configured to read and write a respective logic state and (2) bit and nbit connections (differential and complimentary) connected to each of the RAM cells. A first multiplexer is designed to multiplex the bit and nbit connections of the first plurality of RAM cell columns. A second multiplexer is configured to multiplex the bit and nbit connections of the second plurality of columns. Decode logic controls the first and second multiplexers, and the decode logic accesses a particular column and cell in one of the first and second pluralities during each memory access. A sense amplifier is configured to read the bit and nbit connections of the first and second pluralities via respectively the first and second multiplexers. The sense amplifier is designed to output a logic state from any of the cells based upon a voltage differential and a polarity between the bit and nbit connections of any of the columns. A write driver is configured to write the bit and nbit connections of the first and second plurality via respectively the first and second multiplexers. The write driver drives a logic state onto any of the cells based upon the voltage differential and the polarity between the bit and nbit connections of any of the columns.

摘要翻译： 改进的随机存取存储器（RAM）系统提高了速度并降低了与RAM相关联的功耗和逻辑复杂度。 RAM系统包括第一和第二多个RAM单元列。 每个列包括（1）至少一个RAM单元，每个RAM单元被配置为读取和写入相应的逻辑状态，以及（2）连接到每个RAM单元的位和n位连接（差分和互补）。 第一多路复用器被设计为复用第一多个RAM单元列的位和n位连接。 第二多路复用器被配置为复用第二多个列的位和n位连接。 解码逻辑控制第一和第二多路复用器，并且解码逻辑在每个存储器访问期间访问第一和第二多个之一中的特定列和单元。 读出放大器被配置为分别经由第一和第二多路复用器读取第一和第二多个的位和n位连接。 感测放大器被设计为基于任何列的电压差和位和n位连接之间的极性从任何单元输出逻辑状态。 写入驱动器被配置为分别写入第一和第二多个通道的位和n位连接分别为第一和第二多路复用器。 写入驱动器基于任何列的电压差和位和n位连接之间的极性将逻辑状态驱动到任何单元上。

公开(公告)号：US06944807B2

公开(公告)日：2005-09-13

申请号：US10107291

申请日：2002-03-25

申请人： J. Michael Hill ,  Jonathan E. Lachman ,  Warren K Howlett

发明人： J. Michael Hill ,  Jonathan E. Lachman ,  Warren K Howlett

IPC分类号： G11C29/00

CPC分类号： G11C29/88 ,  G11C15/00 ,  G11C29/883

摘要： The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

摘要翻译： 本发明提供一种用于仅使用可用片上高速缓存的一部分来获得全功能微处理器的电路和方法。 测试片上缓存的存储器子阵列以确定哪些子阵列是有效的。 在确定哪些子阵列是有效的之后，选择一组构成高速缓存的二进制分数的子阵列。 CPU被初始化以适应与所选子阵列的大小相对应的较小的地址空间。 最后，一组信号被编程为允许CPU访问所选择的子阵列。

公开(公告)号：US07152192B2

公开(公告)日：2006-12-19

申请号：US11039666

申请日：2005-01-20

申请人： Karl P. Brummel ,  Todd Mellinger ,  J. Michael Hill

发明人： Karl P. Brummel ,  Todd Mellinger ,  J. Michael Hill

IPC分类号： G11C29/00 ,  G11C7/00 ,  G06F11/00

CPC分类号： G11C29/26 ,  G11C29/40 ,  G11C2029/2602 ,  G11C2029/3202

摘要： A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit comparison in the corresponding data word comparator; and reading the column status bits of each on-chip data word comparator.

摘要翻译： 一种并行地测试集成电路的多个存储块的方法，其中每个存储器块包括行和列阵列中的数据位存储单元，并且其中每行存储单元可寻址以存储具有 由阵列的列数确定的宽度包括以下步骤：将测试数据字并行地写入多个存储块的行; 从多个存储块的行并行地读取测试数据字到相应的多个片上数据字比较器; 呈现与多个片上数据字比较器并行的相应预期数据字，以便与相应存储块的读出数据字进行比较; 同时比较相应数据位比较器中读出的数据字和预期数据字的相应数据位，以产生每个数据位比较的列状态位; 在对应的数据字比较器中锁存不匹配位比较的列状态位; 并读取每个片上数据字比较器的列状态位。

公开(公告)号：US06940778B2

公开(公告)日：2005-09-06

申请号：US10697679

申请日：2003-10-29

申请人： Todd W. Mellinger ,  J. Michael Hill ,  Jonathan E. Lachman

发明人： Todd W. Mellinger ,  J. Michael Hill ,  Jonathan E. Lachman

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C11/00

CPC分类号： G11C5/14

摘要： An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vt from VDD to the positive voltage supply node of the memory cells.

摘要翻译： 本发明的实施例提供了一种用于降低存储器单元中的功率的电路。 电路的输入端连接到存储单元的字线。 当字线有效时，电路的输出将VDD附近的电压施加到存储单元的正电压供应节点。 当字线不活动时，电路的输出将从VDD降低至少一个V SUB的电压到存储单元的正电压供应节点。

公开(公告)号：US06380779B1

公开(公告)日：2002-04-30

申请号：US09903927

申请日：2001-07-12

申请人： Jonathan E. Lachman ,  J. Michael Hill ,  Jim Dale Peterson

发明人： Jonathan E. Lachman ,  J. Michael Hill ,  Jim Dale Peterson

IPC分类号： H03K3037

CPC分类号： H03K3/033 ,  H03K3/355

摘要： An edge-triggered, self-resetting pulse generator where a pulse is initiated by a voltage transition and is reset using feedback from the output. A voltage transition is presented at one input of a two-input NOR gate and at the input of a circuit with three inverters in series. The output from the circuit with three inverters in series connects to the second input of the two-input NOR gate. This combination creates a voltage pulse that drives a transfer FET. The transfer FET creates a voltage on a latch. The latch stores the voltage presented on the input and then drives a delay-chain with an odd number of inverters. The output of the delay-chain drives a second transfer FET that resets the latch.

摘要翻译： 边沿触发的自复位脉冲发生器，其中脉冲由电压转换启动，并使用来自输出的反馈进行复位。 在双输入NOR门的一个输入端和具有串联的三个反相器的电路的输入处呈现电压转换。 具有串联的三个反相器的电路的输出连接到双输入NOR门的第二个输入。 该组合产生驱动传输FET的电压脉冲。 转移FET在锁存器上产生电压。 锁存器存储输入端的电压，然后用奇数个逆变器驱动延迟链。 延迟链的输出驱动复位锁存器的第二个传输FET。

公开(公告)号：US07284168B2

公开(公告)日：2007-10-16

申请号：US11043377

申请日：2005-01-26

申请人： J. Michael Hill ,  Todd Mellinger ,  David Thomas Newsome

发明人： J. Michael Hill ,  Todd Mellinger ,  David Thomas Newsome

IPC分类号： G11C29/00

CPC分类号： G11C17/143 ,  G11C17/165 ,  G11C29/24

摘要： System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die.

摘要翻译： 包括：识别封装的集成电路管芯的冗余RAM中的故障元件的系统和方法，该封装的随机存取存储器（RAM）冗余集成电路管芯包括： 并用封装的集成电路管芯的冗余RAM中的冗余元件替换故障元件。

公开(公告)号：US06321320B1

公开(公告)日：2001-11-20

申请号：US09183536

申请日：1998-10-30

申请人： Jay Fleischman ,  Jeffery C Brauch ,  J. Michael Hill

发明人： Jay Fleischman ,  Jeffery C Brauch ,  J. Michael Hill

IPC分类号： G06F1700

CPC分类号： G11C29/028 ,  G11C29/16 ,  G11C2029/5002

摘要： A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

摘要翻译： 高度灵活和复杂的BIST引擎提供片上存储器阵列的高速访问，测试，表征和监控，而与其他芯片电路（如CPU内核）无关。 每个BIST引擎具有主控制块，至少一个地址生成块具有地址本地控制块和一个或多个地址数据生成块，以及至少一个具有数据本地控制块和一个或多个数据生成的数据生成块 块。 每个本地地址和数据控制块被独立编程，以分别由单独地址和数据生成块执行的操作。 主控制块又控制本地地址和数据控制块的操作，以实现对片上存储器阵列的期望的测试，访问和监视。

公开(公告)号：US06314039B1

公开(公告)日：2001-11-06

申请号：US09578968

申请日：2000-05-25

申请人： J. Michael Hill ,  Jonathan E. Lachman ,  Robert McFarland

发明人： J. Michael Hill ,  Jonathan E. Lachman ,  Robert McFarland

IPC分类号： G11C700

CPC分类号： G11C7/06

摘要： A circuit and method characterizes a sense amplifier, such as the type utilized in computer memory systems. The sense amplifier characterization circuit comprises a sense amplifier having one or more inputs and an output, a BIT line connected to one of the one or more inputs of the sense amplifier, a register connected to the output of the sense amplifier; and control logic connected to the BIT line. Optionally, the register is further connected to the control logic, and the register is a scan register connectable to a tester. Preferably, the sense amplifier is a differential sense amplifier, and the circuit further comprises a complement BIT line connected to one of the one or more inputs of the sense amplifier. The method produces one or more signals like an output of a memory cell, operates one or more sense amplifier to produce one or more output states on the basis of the one or more signals, and records the one or more output states. Optionally, the method also records data related to the one or more signals. In one mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be a static value during the operating step. In another mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be alternating values during the operating step. The method further determines, on the basis of the one or more output states, whether the sense amplifier is acceptable, and if acceptable, the sense amplifier is utilized in a memory system.

摘要翻译： 电路和方法表征了读出放大器，例如在计算机存储器系统中使用的类型。 感测放大器表征电路包括具有一个或多个输入和输出的读出放大器，连接到读出放大器的一个或多个输入中的一个的BIT线，连接到读出放大器的输出的寄存器; 和连接到BIT线的控制逻辑。 可选地，寄存器还连接到控制逻辑，并且寄存器是可连接到测试器的扫描寄存器。 优选地，读出放大器是差分读出放大器，并且该电路还包括连接到读出放大器的一个或多个输入中的一个的补码BIT线。 该方法产生一个或多个信号，如存储器单元的输出，操作一个或多个读出放大器，以基于一个或多个信号产生一个或多个输出状态，并记录一个或多个输出状态。 可选地，该方法还记录与一个或多个信号有关的数据。 在一种操作模式中，该方法在操作步骤期间将一个或多个信号的电压（如存储器单元的输出）设置为静态值。 在另一种操作模式中，该方法在操作步骤期间将一个或多个信号的电压（如存储器单元的输出）设置为交替值。 该方法还基于一个或多个输出状态来确定读出放大器是否可接受，并且如果可接受，则在存储器系统中使用读出放大器。

公开(公告)号：US07055074B2

公开(公告)日：2006-05-30

申请号：US09842333

申请日：2001-04-25

申请人： Brian William Hughes ,  J. Michael Hill ,  Warren Kurt Howlett

发明人： Brian William Hughes ,  J. Michael Hill ,  Warren Kurt Howlett

IPC分类号： G11C29/00

CPC分类号： G11C29/72

摘要： The present invention is directed to a system and method which manages one or more errors in a plurality of elements. The invention tests an element of the plurality of elements and detects the error in one of the elements. The invention then repairs a group of N elements, wherein N is greater than one and the group of N elements includes the element with the error. The invention inhibits subsequent repairs of the group of N elements.

公开(公告)号：US06301140B1

公开(公告)日：2001-10-09

申请号：US09697746

申请日：2000-10-25

申请人： Jonathan E. Lachman ,  J. Michael Hill ,  Todd W. Mellinger

发明人： Jonathan E. Lachman ,  J. Michael Hill ,  Todd W. Mellinger

IPC分类号： G11C1500

CPC分类号： G11C15/04

摘要： A content addressable memory, CAM, cell wherein the only compare-transfer FETS used are NFETs. The gates of the NFET compare-transfer FETS are driven to a voltage above the positive power supply, VDD. By precharging the bitlines to the negative power supply voltage, GND, the gate of one of the compare-transfer NFETS is driven above VDD when a bitline transitions from a “low” value to a “high” value. The capacitance between the bitline being driven high and the gate of a compare-transfer NFET couples the gate higher than VDD. This bootstrapping technique improves the compare access time of a CAM. In addition, this technique reduces the capacitance on the bitlines resulting in faster read and write access times and reduces the physical size of the CAM.

摘要翻译： 内容可寻址存储器CAM单元，其中仅使用比较传输FETS是NFET。 NFET比较传输FETS的栅极被驱动到高于正电源VDD的电压。 通过将位线预充电到负电源电压GND，当位线从“低”值转换到“高”值时，比较传输NFET中的一个的栅极被驱动到VDD以上。 驱动高电平的位线和比较传输NFET的栅极之间的电容使栅极高于VDD。 这种自举技术提高了CAM的比较访问时间。 此外，该技术减少了位线上的电容，从而实现更快的读取和写入访问时间，并降低了CAM的物理尺寸。