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公开(公告)号：US06380779B1
公开(公告)日：2002-04-30
申请号：US09903927
申请日：2001-07-12
IPC分类号： H03K3037
摘要： An edge-triggered, self-resetting pulse generator where a pulse is initiated by a voltage transition and is reset using feedback from the output. A voltage transition is presented at one input of a two-input NOR gate and at the input of a circuit with three inverters in series. The output from the circuit with three inverters in series connects to the second input of the two-input NOR gate. This combination creates a voltage pulse that drives a transfer FET. The transfer FET creates a voltage on a latch. The latch stores the voltage presented on the input and then drives a delay-chain with an odd number of inverters. The output of the delay-chain drives a second transfer FET that resets the latch.
摘要翻译： 边沿触发的自复位脉冲发生器，其中脉冲由电压转换启动，并使用来自输出的反馈进行复位。 在双输入NOR门的一个输入端和具有串联的三个反相器的电路的输入处呈现电压转换。 具有串联的三个反相器的电路的输出连接到双输入NOR门的第二个输入。 该组合产生驱动传输FET的电压脉冲。 转移FET在锁存器上产生电压。 锁存器存储输入端的电压，然后用奇数个逆变器驱动延迟链。 延迟链的输出驱动复位锁存器的第二个传输FET。
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公开(公告)号：US06314039B1
公开(公告)日：2001-11-06
申请号：US09578968
申请日：2000-05-25
IPC分类号： G11C700
CPC分类号： G11C7/06
摘要： A circuit and method characterizes a sense amplifier, such as the type utilized in computer memory systems. The sense amplifier characterization circuit comprises a sense amplifier having one or more inputs and an output, a BIT line connected to one of the one or more inputs of the sense amplifier, a register connected to the output of the sense amplifier; and control logic connected to the BIT line. Optionally, the register is further connected to the control logic, and the register is a scan register connectable to a tester. Preferably, the sense amplifier is a differential sense amplifier, and the circuit further comprises a complement BIT line connected to one of the one or more inputs of the sense amplifier. The method produces one or more signals like an output of a memory cell, operates one or more sense amplifier to produce one or more output states on the basis of the one or more signals, and records the one or more output states. Optionally, the method also records data related to the one or more signals. In one mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be a static value during the operating step. In another mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be alternating values during the operating step. The method further determines, on the basis of the one or more output states, whether the sense amplifier is acceptable, and if acceptable, the sense amplifier is utilized in a memory system.
摘要翻译： 电路和方法表征了读出放大器，例如在计算机存储器系统中使用的类型。 感测放大器表征电路包括具有一个或多个输入和输出的读出放大器，连接到读出放大器的一个或多个输入中的一个的BIT线，连接到读出放大器的输出的寄存器; 和连接到BIT线的控制逻辑。 可选地，寄存器还连接到控制逻辑，并且寄存器是可连接到测试器的扫描寄存器。 优选地，读出放大器是差分读出放大器，并且该电路还包括连接到读出放大器的一个或多个输入中的一个的补码BIT线。 该方法产生一个或多个信号，如存储器单元的输出，操作一个或多个读出放大器，以基于一个或多个信号产生一个或多个输出状态，并记录一个或多个输出状态。 可选地，该方法还记录与一个或多个信号有关的数据。 在一种操作模式中，该方法在操作步骤期间将一个或多个信号的电压（如存储器单元的输出）设置为静态值。 在另一种操作模式中，该方法在操作步骤期间将一个或多个信号的电压（如存储器单元的输出）设置为交替值。 该方法还基于一个或多个输出状态来确定读出放大器是否可接受，并且如果可接受，则在存储器系统中使用读出放大器。
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3.发明授权Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arrays 有权通过使用嵌入式存储器阵列的分数部分来实现更高产品产量的方法和装置公开(公告)号：US06944807B2
公开(公告)日：2005-09-13
申请号：US10107291
申请日：2002-03-25
IPC分类号： G11C29/00
CPC分类号： G11C29/88 , G11C15/00 , G11C29/883
摘要： The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.
摘要翻译： 本发明提供一种用于仅使用可用片上高速缓存的一部分来获得全功能微处理器的电路和方法。 测试片上缓存的存储器子阵列以确定哪些子阵列是有效的。 在确定哪些子阵列是有效的之后，选择一组构成高速缓存的二进制分数的子阵列。 CPU被初始化以适应与所选子阵列的大小相对应的较小的地址空间。 最后，一组信号被编程为允许CPU访问所选择的子阵列。
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公开(公告)号：US06301140B1
公开(公告)日：2001-10-09
申请号：US09697746
申请日：2000-10-25
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A content addressable memory, CAM, cell wherein the only compare-transfer FETS used are NFETs. The gates of the NFET compare-transfer FETS are driven to a voltage above the positive power supply, VDD. By precharging the bitlines to the negative power supply voltage, GND, the gate of one of the compare-transfer NFETS is driven above VDD when a bitline transitions from a “low” value to a “high” value. The capacitance between the bitline being driven high and the gate of a compare-transfer NFET couples the gate higher than VDD. This bootstrapping technique improves the compare access time of a CAM. In addition, this technique reduces the capacitance on the bitlines resulting in faster read and write access times and reduces the physical size of the CAM.
摘要翻译： 内容可寻址存储器CAM单元，其中仅使用比较传输FETS是NFET。 NFET比较传输FETS的栅极被驱动到高于正电源VDD的电压。 通过将位线预充电到负电源电压GND，当位线从“低”值转换到“高”值时，比较传输NFET中的一个的栅极被驱动到VDD以上。 驱动高电平的位线和比较传输NFET的栅极之间的电容使栅极高于VDD。 这种自举技术提高了CAM的比较访问时间。 此外，该技术减少了位线上的电容，从而实现更快的读取和写入访问时间，并降低了CAM的物理尺寸。
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公开(公告)号：US06275442B1
公开(公告)日：2001-08-14
申请号：US09572042
申请日：2000-05-16
IPC分类号： G11C800
摘要： A decoder circuit in a memory system accepts as inputs a clock signal and a plurality of address lines and produces as outputs a plurality of decode lines, such as word lines. The decoder circuit comprises a plurality of pre-decoding circuits, a plurality of latches, and a plurality of AND gates. Each pre-decoding circuit is connected to the clock signal and a unique combination of a subset of the plurality of address lines and their complements. Each pre-decoding circuit produces an output that is set in response to a unique state of the respective subset of the plurality of address lines. Each latch input is connected to an output of a respective one of the plurality of pre-decoding circuits. Each latch output is connected to an AND gate input, and each AND gate output is one of the plurality of decode lines. In another sense, the decoder comprises one or more stages of decoding logic and a set of latches. A first stage of decoding logic accepts the decoder inputs. The outputs of each non-final stage is an input to a subsequent stage. The set of latches are connected to the outputs of a particular non-final stage. A method for using the decoder processes a set of input signals, whereby a set of processed signals are generated. The method latches the processed signals. The latched signals are intermediate signals in a decoding operation, and the method further processes the intermediate signals so as to complete the decoding operation.
摘要翻译： 存储器系统中的解码器电路接收时钟信号和多个地址线作为输入，并且产生诸如字线的多条解码线作为输出。 解码器电路包括多个预解码电路，多个锁存器和多个与门。 每个预解码电路连接到时钟信号和多个地址线的子集及其补码的唯一组合。 每个预解码电路产生响应于多个地址线的相应子集的唯一状态设置的输出。 每个锁存器输入连接到多个预解码电路中的相应一个的输出端。 每个锁存器输出连接到与门输入，每个与门输出是多条译码线之一。 在另一个意义上，解码器包括解码逻辑和一组锁存器的一个或多个阶段。 解码逻辑的第一阶段接受解码器输入。 每个非最后阶段的输出是后续阶段的输入。 锁存器组连接到特定非最终级的输出端。 一种使用解码器的方法处理一组输入信号，从而产生一组处理的信号。 该方法锁存已处理的信号。 锁存信号是解码操作中的中间信号，并且该方法进一步处理中间信号以完成解码操作。
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6.发明授权System and method for reducing leakage in memory cells using wordline control 有权使用字线控制减少存储单元泄漏的系统和方法公开(公告)号：US06940778B2
公开(公告)日：2005-09-06
申请号：US10697679
申请日：2003-10-29
CPC分类号： G11C5/14
摘要： An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vt from VDD to the positive voltage supply node of the memory cells.
摘要翻译： 本发明的实施例提供了一种用于降低存储器单元中的功率的电路。 电路的输入端连接到存储单元的字线。 当字线有效时，电路的输出将VDD附近的电压施加到存储单元的正电压供应节点。 当字线不活动时，电路的输出将从VDD降低至少一个V SUB的电压到存储单元的正电压供应节点。
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公开(公告)号：US06836871B2
公开(公告)日：2004-12-28
申请号：US10282478
申请日：2002-10-29
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5036
摘要： A system and method for generating dynamic circuit design guidelines is disclosed comprising modeling a dynamic circuit using one of a plurality of modeling circuit types, simulating the modeled dynamic circuit, extracting selected information from raw data measured during the simulating step, and analyzing the selected information to create the dynamic circuit design guidelines.
摘要翻译： 公开了一种用于产生动态电路设计指南的系统和方法，其包括使用多个建模电路类型之一对动态电路进行建模，模拟所建模的动态电路，从在模拟步骤期间测量的原始数据中提取所选择的信息，以及分析所选择的信息 制定动态电路设计指南。
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公开(公告)号：US06271568B1
公开(公告)日：2001-08-07
申请号：US08999346
申请日：1997-12-29
IPC分类号： H01L2776
CPC分类号： G11C11/4125
摘要： An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell. At all other times, no voltage is applied to the interconnect. As such, the resistance value of the doped resistor polysilicon region remains at a relatively high value, thereby providing for a high RC time delay and increased immunity to soft errors or single event upsets which may be caused by ionizing radiation.
摘要翻译： SRAM单元包括六个晶体管和两个可变电阻器。 第一对晶体管形成第一反相器，而第二对晶体管形成第二反相器。 剩余的两个晶体管是通过晶体管。 逆变器通过可变电阻交叉耦合，形成存储二进制逻辑状态的触发电路。 可变电阻器通过掺杂多晶硅层的一部分而形成。 掺杂多晶硅电阻器上面是薄的氧化物层。 设置在氧化物层之上的是通过金属化连接的铝或多晶硅的薄层。 当向金属化施加正电压时，电子在掺杂多晶硅电阻器中累积，从而降低多晶硅区域的电阻值。 当需要将数据写入SRAM单元时，在写入周期期间将该电压施加到互连。 多晶硅电阻器的降低的电阻值允许SRAM单元的相对较快的写入时间。 在所有其他时间，没有电压施加到互连。 因此，掺杂电阻器多晶硅区域的电阻值保持在相对较高的值，从而提供高RC时间延迟和增加对可能由电离辐射引起的软错误或单事件扰乱的免疫力。
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公开(公告)号：US06931607B2
公开(公告)日：2005-08-16
申请号：US10282342
申请日：2002-10-29
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04 , H01L27/12 , H03K19/096 , H03K19/00
CPC分类号： G06F17/5045
摘要： A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.
摘要翻译： 公开了一种用于设计绝缘体上硅（SOI）工艺中的动态电路的系统和方法，包括以下步骤：使用至少一个逻辑电路表示动态电路，其中所述至少一个逻辑电路选自 ：具有DNG场效应晶体管（FET）的OR电路，OR电路和AND电路，并且其中根据组中的每个电路的体电压特性来选择至少一个逻辑电路。
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公开(公告)号：US06580635B1
公开(公告)日：2003-06-17
申请号：US10133946
申请日：2002-04-25
申请人： Todd W. Mellinger , Jonathan E. Lachman , John Wuu
发明人： Todd W. Mellinger , Jonathan E. Lachman , John Wuu
IPC分类号： G11C1140
摘要： During read operations of a column of RAM cells, a bitline is electrically broken into two sections. This reduces the capacitance that needs to be discharged by the RAM cell itself. A buffer is used during the read operation to relay data from one part of the split bitline to the other. A weak pullup path is also provided to hold the non-driven end of the line in a stable condition. During non-read operations, the two sections of bitline are electrically connected.
摘要翻译： 在一列RAM单元的读操作期间，位线被电分为两部分。 这就降低了RAM单元本身需要放电的电容。 在读取操作期间使用缓冲器将数据从分割位线的一部分中继到另一部分。 还提供弱上拉路径以将线的非驱动端保持在稳定状态。 在非读取操作期间，位线的两个部分电连接。
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