利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

81 条记录 (耗时 0.024 秒)

    Detecting digital radio signals
    1.
    发明授权
    Detecting digital radio signals 有权
    检测数字无线电信号

    公开(公告)号：US08774328B2

    公开(公告)日：2014-07-08

    申请号：US12894316

    申请日：2010-09-30

    申请人： Javier Elenes ,  Brian D. Green ,  Michael R. May

    发明人： Javier Elenes ,  Brian D. Green ,  Michael R. May

    IPC分类号： H03D1/00

    CPC分类号： H04B1/086 ,  H04H20/30 ,  H04H60/12 ,  H04H2201/18 ,  H04L25/03834 ,  H04L27/0008 ,  H04W52/0229 ,  Y02D70/00

    摘要： In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

    摘要翻译： 在一个实施例中，接收器前端电路可以接收和处理多个射频（RF）信号并输出​​与这些信号对应的下变频信号。 反过来，多个信号处理器可以耦合到该前端。 具体地，第一信号处理器可以接收并处理下变频信号以输出从第一RF信号的内容获得的第一信号，并且第二信号处理器可以接收并处理下变频信号以输出从第二RF信号的内容获得的第二信号 射频信号。 此外，该装置可以包括耦合到接收器前端电路的检测电路，以检测至少第二信号的存在，并使第二信号处理器能够响应于检测到的存在。

    DETECTING DIGITAL RADIO SIGNALS
    2.
    发明申请
    DETECTING DIGITAL RADIO SIGNALS 有权
    检测数字无线电信号

    公开(公告)号：US20120082271A1

    公开(公告)日：2012-04-05

    申请号：US12894316

    申请日：2010-09-30

    申请人： JAVIER ELENES ,  Brian D. Green ,  Michael R. May

    发明人： JAVIER ELENES ,  Brian D. Green ,  Michael R. May

    IPC分类号： H04L27/06

    CPC分类号： H04B1/086 ,  H04H20/30 ,  H04H60/12 ,  H04H2201/18 ,  H04L25/03834 ,  H04L27/0008 ,  H04W52/0229 ,  Y02D70/00

    摘要： In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

    摘要翻译： 在一个实施例中，接收器前端电路可以接收和处理多个射频（RF）信号并输出​​与这些信号对应的下变频信号。 反过来，多个信号处理器可以耦合到该前端。 具体地，第一信号处理器可以接收并处理下变频信号以输出从第一RF信号的内容获得的第一信号，并且第二信号处理器可以接收并处理下变频信号以输出从第二RF信号的内容获得的第二信号 射频信号。 此外，该装置可以包括耦合到接收器前端电路的检测电路，以检测至少第二信号的存在，并使第二信号处理器能够响应于检测到的存在。

    Statistical Gain Control In A Receiver
    5.
    发明申请
    Statistical Gain Control In A Receiver 有权
    接收器中的统计增益控制

    公开(公告)号：US20120244825A1

    公开(公告)日：2012-09-27

    申请号：US13070683

    申请日：2011-03-24

    申请人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

    发明人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

    IPC分类号： H04B17/00

    CPC分类号： H03G3/3073 ,  H03G3/3052 ,  H04B17/318

    摘要： A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

    摘要翻译： 在接收机中接收射频（RF）信号，并且可以获得基于来自信号的信息的各种计数。 可以在累积窗口期间累积超过第一和第二阈值的RF信号的多个样本的计数。 从这些计数中的第一个可以确定计数是否超过对应于第一预定计数值的第一度量，如果是，则可以减小RF增益元件的增益。 从这些计数中的第二个可以确定该计数是否超过对应于第二预定计数值的第二度量，如果不是，则可以增加增益。

    Statistical gain control in a receiver
    6.
    发明授权
    Statistical gain control in a receiver 有权
    接收机的统计增益控制

    公开(公告)号：US09172344B2

    公开(公告)日：2015-10-27

    申请号：US13070683

    申请日：2011-03-24

    申请人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

    发明人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

    IPC分类号： H04B1/06 ,  H04B7/00 ,  H03G3/30 ,  H04B17/318

    CPC分类号： H03G3/3073 ,  H03G3/3052 ,  H04B17/318

    摘要： A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

    摘要翻译： 在接收机中接收射频（RF）信号，并且可以获得基于来自信号的信息的各种计数。 可以在累积窗口期间累积超过第一和第二阈值的RF信号的多个样本的计数。 从这些计数中的第一个可以确定计数是否超过对应于第一预定计数值的第一度量，如果是，则可以减小RF增益元件的增益。 从这些计数中的第二个可以确定该计数是否超过对应于第二预定计数值的第二度量，如果不是，则可以增加增益。

    Systems and methods for controlling integrated circuit operation with below ground pin voltage
    7.
    发明申请
    Systems and methods for controlling integrated circuit operation with below ground pin voltage 有权
    用低于地脚电压控制集成电路运行的系统和方法

    公开(公告)号：US20110122671A1

    公开(公告)日：2011-05-26

    申请号：US12592240

    申请日：2009-11-20

    申请人： Michael R. May

    发明人： Michael R. May

    IPC分类号： G11C7/10 ,  G11C17/00 ,  G05F1/00

    CPC分类号： G11C29/46 ,  G11C5/143 ,  G11C17/146 ,  G11C17/165 ,  G11C17/18

    摘要： Systems and methods for controlling operation of an integrated circuit by applying below ground voltage to one or more pins of the integrated circuit, and in which the application of a below ground pin voltage may be employed as an initiator of (or condition for) a given mode of circuit operation in a manner that prevents the inadvertent initiation of the given mode of operation that may otherwise occur due to accidental application of an above ground voltage to one or more pins of the integrated circuit.

    摘要翻译： 通过向集成电路的一个或多个引脚施加低于地电压的控制集成电路的操作的系统和方法，并且其中施加低于接地引脚电压的可以用作给定的（或）条件的引发者 电路操作的模式，以防止由于将集成电路的一个或多个引脚意外地施加上述地电压而导致的给定操作模式的意外启动。

    Adjust switching rate of a power supply to mitigate interference
    8.
    发明授权
    Adjust switching rate of a power supply to mitigate interference 有权
    调整电源的开关速率以减轻干扰

    公开(公告)号：US07720456B2

    公开(公告)日：2010-05-18

    申请号：US11355477

    申请日：2006-02-16

    申请人： Michael R. May ,  Marcus W. May ,  Matthew Brady Henson

    发明人： Michael R. May ,  Marcus W. May ,  Matthew Brady Henson

    IPC分类号： H04B1/10

    CPC分类号： H04B15/005 ,  H04B2215/068

    摘要： A method for mitigating interference from a switched-mode power supply begins by comparing a channel of interest of a plurality of channels with a switching rate of a switch-mode power supply. The method continues when the channel of interest compares unfavorably to the switching rate by adjusting the switching rate of the switch-mode power supply until the channel of interest compares favorably to the switching rate.

    摘要翻译： 通过将多个信道的感兴趣信道与开关模式电源的切换速率进行比较，开始减少来自开关模式电源的干扰的方法。 当感兴趣的信道通过调整开关模式电源的切换速率直到感兴趣的信道与切换速率有利地相比，当感兴趣的信道与切换速率不利地相比时，继续该方法。

    Radio receiver, system on a chip integrated circuit and methods for use therewith
    9.
    发明授权
    Radio receiver, system on a chip integrated circuit and methods for use therewith 有权
    无线电接收机，片上系统集成电路及其使用方法

    公开(公告)号：US07672403B2

    公开(公告)日：2010-03-02

    申请号：US11287570

    申请日：2005-11-22

    申请人： Michael R. May ,  Erich Lowe

    发明人： Michael R. May ,  Erich Lowe

    IPC分类号： H03K9/00 ,  H04L27/00

    CPC分类号： H03D3/007 ,  H03J1/0008

    摘要： A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

    摘要翻译： 一种片上集成电路系统包括第一同相数字子模块和第一正交相位数字子模块，使得第一同相数字子模块和第一正交相位数字子模块可操作以基于at产生至少一个输出信号 至少一个输入信号。 数字时钟发生器产生具有在预定周期内具有多个第一同相数字时钟周期的第一同相数字时钟信号和在预定周期内具有多个第一正交相位数字时钟周期的第一正交相位数字时钟信号 。 多个第一同相数字时钟周期在预定周期内与多个第一正交相位数字时钟周期基本交错。

    Digital clock controller, radio receiver, and methods for use therewith
    10.
    发明授权
    Digital clock controller, radio receiver, and methods for use therewith 失效
    数字时钟控制器，无线电接收器及其使用方法

    公开(公告)号：US07620131B2

    公开(公告)日：2009-11-17

    申请号：US11287549

    申请日：2005-11-22

    申请人： Michael R. May ,  Erich Lowe

    发明人： Michael R. May ,  Erich Lowe

    IPC分类号： H04B1/10

    CPC分类号： H04B15/02 ,  H04B2215/064

    摘要： A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.

    摘要翻译： 数字时钟发生器包括基本时钟发生器，用于响应于控制信号而以可变的基本时钟频率产生基本时钟信号。 数字时钟控制器在预定时间段内产生具有基本恒定数量的时钟周期数的数字时钟信号。