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公开(公告)号：US07890071B2
公开(公告)日：2011-02-15
申请号：US11126554
申请日：2005-05-11
IPC分类号： H04B1/38
CPC分类号： H04H40/45
摘要： A handheld audio system includes a radio signal decoder integrated circuit (IC) and a digital audio processing integrated circuit. The radio signal decoder integrated circuit produces a digital left channel signal and a digital right channel signal from a received radio signal in accordance with an enable signal and also produces a system clock. The digital audio processing integrated circuit includes a DC-to-DC converter and a processing module. The DC-to-DC converter is operably coupled to produce at least one power supply voltage based on the system clock. The processing module is operably coupled to produce the enable signal when the at least one power supply voltage has reached a desired level and to produce audio signals for audio playback from at least one of the digital left and right channel signals and a stored digital audio file.
摘要翻译： 手持音频系统包括无线电信号解码器集成电路（IC）和数字音频处理集成电路。 无线电信号解码器集成电路根据使能信号从接收的无线电信号产生数字左声道信号和数字右声道信号，并且还产生系统时钟。 数字音频处理集成电路包括DC-DC转换器和处理模块。 DC-DC转换器可操作地耦合以基于系统时钟产生至少一个电源电压。 当至少一个电源电压已经达到期望的水平并且从数字左声道信号和右声道信号中的至少一个产生用于音频回放的音频信号时，处理模块可操作地耦合以产生使能信号，并且存储的数字音频文件 。
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公开(公告)号：US07720456B2
公开(公告)日：2010-05-18
申请号：US11355477
申请日：2006-02-16
IPC分类号： H04B1/10
CPC分类号： H04B15/005 , H04B2215/068
摘要： A method for mitigating interference from a switched-mode power supply begins by comparing a channel of interest of a plurality of channels with a switching rate of a switch-mode power supply. The method continues when the channel of interest compares unfavorably to the switching rate by adjusting the switching rate of the switch-mode power supply until the channel of interest compares favorably to the switching rate.
摘要翻译： 通过将多个信道的感兴趣信道与开关模式电源的切换速率进行比较，开始减少来自开关模式电源的干扰的方法。 当感兴趣的信道通过调整开关模式电源的切换速率直到感兴趣的信道与切换速率有利地相比，当感兴趣的信道与切换速率不利地相比时，继续该方法。
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公开(公告)号：US06633187B1
公开(公告)日：2003-10-14
申请号：US09716731
申请日：2000-11-20
申请人： Michael R. May , Marcus W. May
发明人： Michael R. May , Marcus W. May
IPC分类号： H03K302
CPC分类号： G06F1/24 , H03K17/223
摘要： A method and apparatus for enabling a stand-alone integrated circuit (IC) includes processing that begins by establishing an idle state that holds at least a portion of the stand-alone integrated circuit in a reset condition when a power source is operably coupled to the stand-alone integrated circuit. A stand-alone integrated circuit includes generally an on-chip power converter, a reset circuit and some functional circuitry, which may be a microprocessor, digital signal processor digital circuitry, state machine, logic circuitry, analog circuitry, and/or any type of components and/or circuits that perform a desired electrical function. When a power enable signal is received, the on-chip power converter is enabled to generate at least 1 supply from the power source. The processing continues by enabling functionality of the stand-alone integrated circuit when the at least one supply has substantially reached a steady state condition.
摘要翻译： 一种用于使得独立集成电路（IC）能够实现的方法和装置包括当电源可操作地耦合到所述独立集成电路（IC）时，通过建立将独立集成电路的至少一部分保持在复位状态的空闲状态开始的处理 独立集成电路。 独立集成电路通常包括片上功率转换器，复位电路和一些功能电路，其可以是微处理器，数字信号处理器数字电路，状态机，逻辑电路，模拟电路和/或任何类型的 执行所需电功能的组件和/或电路。 当接收到功率使能信号时，芯片上的功率转换器能够从电源产生至少1个电源。 当至少一个电源基本上达到稳定状态时，继续执行独立集成电路的功能。
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公开(公告)号：US07583216B2
公开(公告)日：2009-09-01
申请号：US11863631
申请日：2007-09-28
申请人： Matthew D. Felder , Marcus W. May , Michael R. May
发明人： Matthew D. Felder , Marcus W. May , Michael R. May
IPC分类号： H03M1/66
摘要： A digital to analog converter (DAC) includes at least one digital to analog conversion module and a gated termination. The at least one digital to analog conversion module is coupled to convert at least one bit of a digital signal into an analog signal. The gated termination is coupled to an analog output of the at least one digital to analog conversion module to provide a first termination when a termination selection signal is in a first state and to provide a second termination when the termination selection signal is in a second state.
摘要翻译： 数模转换器（DAC）包括至少一个数模转换模块和门控终端。 所述至少一个数模转换模块被耦合以将数字信号的至少一位转换为模拟信号。 门控终端耦合到至少一个数模转换模块的模拟输出，以在端接选择信号处于第一状态时提供第一终端，并且当终端选择信号处于第二状态时提供第二终端 。
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公开(公告)号：US20090085782A1
公开(公告)日：2009-04-02
申请号：US11863631
申请日：2007-09-28
申请人： Matthew D. Felder , Marcus W. May , Michael R. May
发明人： Matthew D. Felder , Marcus W. May , Michael R. May
摘要： A digital to analog converter (DAC) includes at least one digital to analog conversion module and a gated termination. The at least one digital to analog conversion module is coupled to convert at least one bit of a digital signal into an analog signal. The gated termination is coupled to an analog output of the at least one digital to analog conversion module to provide a first termination when a termination selection signal is in a first state and to provide a second termination when the termination selection signal is in a second state.
摘要翻译： 数模转换器（DAC）包括至少一个数模转换模块和门控终端。 所述至少一个数模转换模块被耦合以将数字信号的至少一位转换为模拟信号。 门控终端耦合到至少一个数模转换模块的模拟输出，以在端接选择信号处于第一状态时提供第一终端，并且当终端选择信号处于第二状态时提供第二终端 。
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公开(公告)号：US20130084818A1
公开(公告)日：2013-04-04
申请号：US13249508
申请日：2011-09-30
申请人： Russell Croman , Christopher S. Gregg , Dan B. Kasha , Michael R. May , John Khoury , Javier Elenes
发明人： Russell Croman , Christopher S. Gregg , Dan B. Kasha , Michael R. May , John Khoury , Javier Elenes
CPC分类号： H04W52/0238 , H04B1/06 , H04W52/0245 , Y02D70/40
摘要： In one embodiment, a method includes receiving and processing an incoming radio frequency (RF) signal in a receiver. Based on this signal, an environmental noise level can be determined, where this level corresponds to environmental noise present in an environment in which the receiver is located. Then, if the environmental noise level is substantially greater than receiver-generated noise, power consumption of at least one analog front end component of the receiver can be reduced.
摘要翻译： 在一个实施例中，一种方法包括在接收机中接收和处理输入射频（RF）信号。 基于该信号，可以确定环境噪声电平，其中该电平对应于存在于接收器所处的环境中的环境噪声。 然后，如果环境噪声电平显着大于接收器产生的噪声，则可以减少接收机的至少一个模拟前端部件的功耗。
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7.发明申请Systems and methods for controlling integrated circuit operation with below ground pin voltage 有权用低于地脚电压控制集成电路运行的系统和方法公开(公告)号：US20110122671A1
公开(公告)日：2011-05-26
申请号：US12592240
申请日：2009-11-20
申请人： Michael R. May
发明人： Michael R. May
CPC分类号： G11C29/46 , G11C5/143 , G11C17/146 , G11C17/165 , G11C17/18
摘要： Systems and methods for controlling operation of an integrated circuit by applying below ground voltage to one or more pins of the integrated circuit, and in which the application of a below ground pin voltage may be employed as an initiator of (or condition for) a given mode of circuit operation in a manner that prevents the inadvertent initiation of the given mode of operation that may otherwise occur due to accidental application of an above ground voltage to one or more pins of the integrated circuit.
摘要翻译： 通过向集成电路的一个或多个引脚施加低于地电压的控制集成电路的操作的系统和方法，并且其中施加低于接地引脚电压的可以用作给定的（或）条件的引发者 电路操作的模式，以防止由于将集成电路的一个或多个引脚意外地施加上述地电压而导致的给定操作模式的意外启动。
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8.发明授权Radio receiver, system on a chip integrated circuit and methods for use therewith 有权无线电接收机，片上系统集成电路及其使用方法公开(公告)号：US07672403B2
公开(公告)日：2010-03-02
申请号：US11287570
申请日：2005-11-22
申请人： Michael R. May , Erich Lowe
发明人： Michael R. May , Erich Lowe
CPC分类号： H03D3/007 , H03J1/0008
摘要： A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.
摘要翻译： 一种片上集成电路系统包括第一同相数字子模块和第一正交相位数字子模块，使得第一同相数字子模块和第一正交相位数字子模块可操作以基于at产生至少一个输出信号 至少一个输入信号。 数字时钟发生器产生具有在预定周期内具有多个第一同相数字时钟周期的第一同相数字时钟信号和在预定周期内具有多个第一正交相位数字时钟周期的第一正交相位数字时钟信号 。 多个第一同相数字时钟周期在预定周期内与多个第一正交相位数字时钟周期基本交错。
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9.发明授权公开(公告)号：US07620131B2
公开(公告)日：2009-11-17
申请号：US11287549
申请日：2005-11-22
申请人： Michael R. May , Erich Lowe
发明人： Michael R. May , Erich Lowe
IPC分类号： H04B1/10
CPC分类号： H04B15/02 , H04B2215/064
摘要： A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.
摘要翻译： 数字时钟发生器包括基本时钟发生器，用于响应于控制信号而以可变的基本时钟频率产生基本时钟信号。 数字时钟控制器在预定时间段内产生具有基本恒定数量的时钟周期数的数字时钟信号。
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公开(公告)号：US07602862B2
公开(公告)日：2009-10-13
申请号：US11237344
申请日：2005-09-28
申请人： Michael R. May , Matthew D. Felder
发明人： Michael R. May , Matthew D. Felder
CPC分类号： H03D3/007
摘要： A mixing module includes a plurality of switched sample modules operably for generating a corresponding plurality of samples of an analog input signal in response to a control signal. A control module generates a mixing sequence and a control signal based on the mixing sequence, the control signal including a sequence of sample positions at a sampling clock rate and a sequence of scale factors, the sequence of scale factors based on an oscillation, wherein the sampling clock has a sample period and wherein the sequence of sample positions repeats at a sample position period greater than a sample interval, the sample interval equal to the sample period times the number of the plurality of switched sample circuits.
摘要翻译： 混合模块包括可操作地用于响应于控制信号产生模拟输入信号的相应多个样本的多个切换采样模块。 控制模块基于混合序列产生混合序列和控制信号，该控制信号包括采样时钟速率的采样位置序列和比例因子序列，基于振荡的比例因子序列，其中， 采样时钟具有采样周期，其中采样位置序列在大于采样间隔的采样位置周期重复，采样间隔等于采样周期乘以多个开关采样电路的数量。
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