公开(公告)号：US20120038590A1

公开(公告)日：2012-02-16

申请号：US12972422

申请日：2010-12-17

申请人： JEE IN KIM ,  Young Seok Ahn ,  Jun Lee ,  Hyung Seok Kim ,  Min Gyu Lim

发明人： JEE IN KIM ,  Young Seok Ahn ,  Jun Lee ,  Hyung Seok Kim ,  Min Gyu Lim

IPC分类号： G06F3/042

CPC分类号： G06F3/0425 ,  G06F2203/04104 ,  G06F2203/04106 ,  G06F2203/04109

摘要： Provided is a tabletop interface system. A tabletop input device diffuses an infrared light emitted based on at least one touch input from a user. A tabletop output device allows the diffused infrared light to pass therethrough to display content information corresponding to at least one touch point. The tabletop recognition device recognizes the at least one touch point by generating a touch image data based on the infrared light passing through the tabletop output device and generates touch point information by using the touch image data. The content server transmits the content information, which corresponds to the touch point information received from the tabletop recognition device, to at least one content client application.

摘要翻译： 提供了一个桌面接口系统。 桌面输入设备基于来自用户的至少一个触摸输入扩散发射的红外光。 桌面输出装置允许扩散红外光通过其中以显示对应于至少一个触摸点的内容信息。 桌面识别装置通过基于穿过桌面输出装置的红外线产生触摸图像数据来识别至少一个触摸点，并且通过使用触摸图像数据生成触摸点信息。 内容服务器将对应于从桌面识别装置接收的触摸点信息的内容信息发送到至少一个内容客户端应用程序。

公开(公告)号：US6124170A

公开(公告)日：2000-09-26

申请号：US17926

申请日：1998-02-03

申请人： Min Gyu Lim ,  Eun Jeong Park

发明人： Min Gyu Lim ,  Eun Jeong Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7883

摘要： A flash memory is disclosed including a second conductivity-type substrate having first conductivity-type first and second impurity regions spaced apart from each other by a predetermined distance; a second conductivity-type floating gate formed above part of the first impurity region; a first conductivity-type floating gate formed over the second conductivity-type floating gate; and an insulating layer and first conductivity-type control gate sequentially formed on the first conductivity-type floating gate.

摘要翻译： 公开了一种闪速存储器，其包括具有彼此隔开预定距离的第一导电类型的第一和第二杂质区的第二导电型衬底; 形成在所述第一杂质区的一部分上方的第二导电型浮栅; 形成在所述第二导电型浮栅上的第一导电型浮栅; 以及依次形成在第一导电型浮栅上的绝缘层和第一导电型控制栅。

公开(公告)号：US06989307B2

公开(公告)日：2006-01-24

申请号：US10803422

申请日：2004-03-18

申请人： Min Gyu Lim

发明人： Min Gyu Lim

IPC分类号： H01L21/8329

CPC分类号： H01L27/11253 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11293

摘要： The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

公开(公告)号：US06734508B2

公开(公告)日：2004-05-11

申请号：US10039364

申请日：2001-11-07

申请人： Min Gyu Lim

发明人： Min Gyu Lim

IPC分类号： H01L2976

CPC分类号： H01L27/11253 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11293

摘要： The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

摘要翻译： 本发明公开了一种与逻辑处理具有优异兼容性并改善存储单元的集成的掩模ROM及其制造方法。 掩模ROM包括：限定了存储单元阵列区域和段选择区域的基板; 第一和第二沟槽分别形成在存储单元阵列区域的外部部分和在段选择区域的掩埋层形成区域的外部; 分别填充第一和第二沟槽的元件隔离膜和隔离图案; 多个掩埋层在第一方向上以预定间隔在基板上对准并被隔离图案包围; 以及沿第二方向排列的多个栅极，以沿正交方向跨过掩埋层。

公开(公告)号：US06518131B1

公开(公告)日：2003-02-11

申请号：US10053381

申请日：2001-11-07

申请人： Min Gyu Lim

发明人： Min Gyu Lim

IPC分类号： H01L218246

CPC分类号： H01L27/11293 ,  H01L27/112

摘要： A method that includes: providing a substrate where a memory cell array region and a peripheral region are defined; forming a buried layer on the substrate; forming a gate material by positioning a gate insulating film on the substrate having the buried layer; forming first gates by covering the peripheral region, and etching the gate material of the memory cell array region according to a photolithography process; forming an insulating pattern on the substrate to fill up a space between the first gates and expose the surfaces of the first gates; forming second gates by covering the memory cell array region, and etching the gate material of the peripheral region according to the photolithography process; and forming a low resistance layer on the first gates, and simultaneously forming a source/drain at both sides of the second gates, by doping an impurity to the substrate having the first and second gates.

摘要翻译： 一种方法，包括：提供定义存储单元阵列区域和外围区域的基板; 在衬底上形成掩埋层; 通过在具有掩埋层的基板上设置栅极绝缘膜来形成栅极材料; 通过覆盖周边区域形成第一栅极，并根据光刻工艺蚀刻存储单元阵列区域的栅极材料; 在所述基板上形成绝缘图案以填充所述第一栅极之间的空间并暴露所述第一栅极的表面; 通过覆盖存储单元阵列区域形成第二栅极，并根据光刻工艺蚀刻外围区域的栅极材料; 在第一栅极上形成低电阻层，同时通过在具有第一和第二栅极的衬底上掺杂杂质，在第二栅极的两侧形成源极/漏极。

公开(公告)号：US06225164B1

公开(公告)日：2001-05-01

申请号：US09642592

申请日：2000-08-22

申请人： Min Gyu Lim

发明人： Min Gyu Lim

IPC分类号： H01L218247

CPC分类号： H01L27/11521

摘要： Semiconductor memory and a method for fabricating the same, in which sides of a floating gate is formed to have a streamlined profile, for improving a device performance, the semiconductor memory including a semiconductor substrate, a plurality of field oxide films formed at fixed intervals in one direction for isolating an active region between adjacent field oxide films, a plurality of control gates formed at fixed intervals in a second direction perpendicular to the field oxide films, a plurality of floating gates respectively formed under the control gates spaced a distance from each other each having edge portions in the second direction with moderate slopes, an interlayer insulating layer formed at interfaces between the floating gate and the control gate, and source/drain formed in surfaces of a semiconductor substrate on both sides of the control gate.

摘要翻译： 半导体存储器及其制造方法，其中浮动栅极的侧面形成为具有流线型的轮廓，用于改善器件性能，半导体存储器包括半导体衬底，以固定间隔形成的多个场氧化膜 用于隔离相邻的场氧化物膜之间的有源区的一个方向，在与场氧化物膜垂直的第二方向上以固定的间隔形成的多个控制栅，分别形成在彼此间隔一定距离的控制栅下方的多个浮置栅 每个具有在第二方向上具有中等斜率的边缘部分，在浮动栅极和控制栅极之间的界面处形成的层间绝缘层，以及形成在控制栅极两侧的半导体衬底的表面中的源极/漏极。

公开(公告)号：US6037221A

公开(公告)日：2000-03-14

申请号：US790859

申请日：1997-02-03

申请人： Sung Chul Lee ,  Min Gyu Lim

发明人： Sung Chul Lee ,  Min Gyu Lim

IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A non-volatile memory device includes a substrate, a projection having two sides formed on the substrate, a floating gate formed on the projection, a control gate formed on the substrate including the floating gate, a first impurity region formed in the substrate extended from one side of the projection, and a second impurity region formed in the substrate at the other side of the projection and in the substrate extended from the other side of the projection.

摘要翻译： 一种非易失性存储器件，包括：衬底，具有形成在衬底上的两侧的突起;形成在该突起上的浮置栅极;形成在该衬底上的控制栅极，该栅极包括该浮动栅极;形成在该衬底中的第一杂质区， 在突起的另一侧和从该突起的另一侧延伸的基板的基板上形成的第二杂质区域。

公开(公告)号：US5773343A

公开(公告)日：1998-06-30

申请号：US512644

申请日：1995-08-08

申请人： Sung Chul Lee ,  Min Gyu Lim

发明人： Sung Chul Lee ,  Min Gyu Lim

IPC分类号： H01L27/112 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L29/42336 ,  H01L29/7883

摘要： A semiconductor device having a recessed channel structure which has a semiconductor region positioned at a level above a channel region, including a first conduction type substrate having a channel region therein, a second conduction type semiconductor region formed on the substrate excluding the channel region, a first insulation film formed on the semiconductor region, a second insulation film formed on a surface between the channel region and the semiconductor region, a first gate formed on a gate insulation film on the channel region, and a dielectric film formed between the first gate and the first insulation film. Also, a method for fabricating a semiconductor device having a recessed structure, including the steps of: forming a second conduction type polysilicon film on a first conduction type substrate; forming a first insulation film on the polysilicon film; forming a semiconductor layer by etching the first insulation film and the underlying polysilicon film; forming a second insulation film on an exposed surface of the substrate between the semiconductor layer and at sides of the semiconductor layer and the first insulation film; forming a first gate on the second insulation film; forming a dielectric film on a surface between the first gate and the second insulation film; and forming a second gate on the dielectric film.

摘要翻译： 一种具有凹陷沟道结构的半导体器件，其具有位于沟道区域上方的半导体区域，包括其中具有沟道区的第一导电型衬底，形成在除了沟道区域之外的衬底上的第二导电型半导体区域， 形成在半导体区域上的第一绝缘膜，形成在沟道区域和半导体区域之间的表面上的第二绝缘膜，形成在沟道区域上的栅极绝缘膜上的第一栅极，以及形成在第一栅极和 第一绝缘膜。 另外，制造具有凹陷结构的半导体器件的方法包括以下步骤：在第一导电型衬底上形成第二导电型多晶硅膜; 在所述多晶硅膜上形成第一绝缘膜; 通过蚀刻第一绝缘膜和下面的多晶硅膜形成半导体层; 在所述半导体层和所述半导体层和所述第一绝缘膜之间的所述衬底的暴露表面上形成第二绝缘膜; 在所述第二绝缘膜上形成第一栅极; 在所述第一栅极和所述第二绝缘膜之间的表面上形成电介质膜; 以及在所述电介质膜上形成第二栅极。