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公开(公告)号:US20230410747A1
公开(公告)日:2023-12-21
申请号:US18334930
申请日:2023-06-14
Applicant: JOLED INC.
Inventor: Hiroshi FUJIMURA , Hitoshi TSUGE
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0819 , G09G2300/0852 , G09G2300/0413 , G09G2320/0247
Abstract: A control method is a method of a display device including a plurality of pixel circuits. Each of the pixel circuits includes a light emitting element, a drive transistor, and a pixel capacitance. The drive transistor includes a gate and a source. A frame period includes a first subframe period and at least one second subframe period. In the first subframe period, the control method includes: (A) applying a first initialization potential to the source; (B) writing a signal into the pixel capacitance; and (C) causing the light emitting element to emit light. In each of the at least one second subframe period, the control method includes: (D) maintaining the light emitting element in a non-emission state; (E) applying a second initialization potential to the source in (D); and (F) causing the light emitting element to emit light.
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公开(公告)号:US20180197464A1
公开(公告)日:2018-07-12
申请号:US15863290
申请日:2018-01-05
Applicant: JOLED INC.
Inventor: Tetsuro YAMAMOTO , Hiroshi FUJIMURA
IPC: G09G3/3208
CPC classification number: G09G3/3208 , G09G3/3233 , G09G3/3266 , G09G2310/0291 , G09G2310/08
Abstract: A drive circuit having an output terminal includes a buffer circuit including a first transistor and a second transistor that are connected in parallel between a power supply and the output terminal. The first transistor and the second transistor are controlled such that after the first transistor and the second transistor are simultaneously turned on, the second transistor is turned off earlier than the first transistor.
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公开(公告)号:US20190305064A1
公开(公告)日:2019-10-03
申请号:US16273156
申请日:2019-02-12
Applicant: JOLED INC.
Inventor: Tokuaki KUNIYOSHI , Naoki ASANO , Ryo KOSHIISHI , Hiroshi FUJIMURA
IPC: H01L27/32 , H01L29/786
Abstract: A semiconductor device includes a base, a first wiring line, a semiconductor film, a second wiring line, an insulating film, and a semiconductor auxiliary layer. The first wiring line is provided in the first, second, and third regions of the base. The semiconductor film has one or more low-resistance regions, is provided between the first wiring line and the base in the first region, and is in contact with the first wiring line in the second region. The second wiring line is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region. The semiconductor auxiliary layer is in contact with the semiconductor film at least in the first region, and assists electrical coupling via the first region.
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