公开(公告)号：US06297133B1

公开(公告)日：2001-10-02

申请号：US09123737

申请日：1998-07-28

申请人： Jacob Chen ,  Tz-Guei Jung

发明人： Jacob Chen ,  Tz-Guei Jung

IPC分类号： H01L21265

CPC分类号： H01L21/823493 ,  H01L27/10844 ,  H01L27/10894

摘要： A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well formed in the present invention has low dosage ions, hence the DRAM formed on the triple well in subsequent process can have a faster refresh time.

摘要翻译： 制造井的方法包括提供p型衬底，然后在p型衬底中以低剂量顺序形成p阱和n-阱的步骤。 此后，使用能量将n型离子掺杂到p阱中。 在本发明中形成的三重阱具有低剂量离子，因此在后续工艺中形成在三阱上的DRAM可以具有更快的刷新时间。

公开(公告)号：US06218239B1

公开(公告)日：2001-04-17

申请号：US09195168

申请日：1998-11-17

申请人： Keh-Ching Huang ,  Wen-Jeng Lin ,  Tz-Guei Jung ,  Jacob Chen

发明人： Keh-Ching Huang ,  Wen-Jeng Lin ,  Tz-Guei Jung ,  Jacob Chen

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L27/10855 ,  H01L28/91

摘要： The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.

摘要翻译： 本发明提供一种在基板上形成用于电容器的底板的制造方法，其中所述基板包括具有栅极和一对源极/漏极区域的MOS晶体管。 冠状导电板形成在绝缘氧化物层和接触插塞上。 冠状导电板穿透绝缘层和阻挡层，其中冠状导电板的底部电连接到接触插塞。 用作DRAM电容器的底板的冠状导电板由硅化钨或氮化钨层和钨层的组合构成。

公开(公告)号：US6060349A

公开(公告)日：2000-05-09

申请号：US152449

申请日：1998-09-14

申请人： Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

发明人： Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

IPC分类号： H01L21/8242

CPC分类号： H01L27/10844 ,  H01L27/10852

摘要： A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.

摘要翻译： 用于制造嵌入式动态随机存取存储器（DRAM）的平面化方法。 在半导体衬底上形成多个金属氧化物半导体（MOS）晶体管和多个电容器之后，在衬底上形成第一层间二电极（ILD）层。 嵌入式DRAM被分成存储区域和逻辑区域。 接下来，进行平坦化。 形成虚设的金属层并与逻辑区域中的MOS晶体管的可互换的源/漏区耦合。 然后在逻辑区域上形成第二ILD层以补偿逻辑区域和存储区域之间的高度差异。 然后，在逻辑区域中形成通孔/插头以延伸第一金属层。 在衬底上形成具有所需接触窗/插塞的第二金属层。

公开(公告)号：US06303455B1

公开(公告)日：2001-10-16

申请号：US09541450

申请日：2000-03-31

申请人： Chia-Hsin Hou ,  Tz-Guei Jung ,  Joe Ko

发明人： Chia-Hsin Hou ,  Tz-Guei Jung ,  Joe Ko

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L28/60

摘要： A method for manufacturing a capacitor is provided in the present invention. The bottom electrode of the capacitor is a polysilicon layer, and the top electrode of the capacitor is a silicide layer. Since depletion regions cannot be generated in the metal layer or the suicide layer, and the resistivity of the metal layer or the silicide layer is smaller than a conventional polysilicon layer, so that operating speed and frequency of the capacitor are both increased.

摘要翻译： 本发明提供一种电容器的制造方法。 电容器的底部电极是多晶硅层，电容器的顶部电极是硅化物层。 由于在金属层或硅化物层中不能产生耗尽区，并且金属层或硅化物层的电阻率比常规多晶硅层小，所以电容器的工作速度和频率都增加。

公开(公告)号：US06309925B1

公开(公告)日：2001-10-30

申请号：US09643211

申请日：2000-08-22

申请人： Tz-Guei Jung ,  Chia-Hsin Hou ,  Joe Ko

发明人： Tz-Guei Jung ,  Chia-Hsin Hou ,  Joe Ko

IPC分类号： H01L218242

CPC分类号： H01L27/0629 ,  H01L28/40

摘要： A method for manufacturing a capacitor. A semiconductor substrate is divided into a peripheral circuit region and a memory cell region. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate outside the isolation structure. A polysilicon layer is formed over the gate oxide layer and the isolation structure. The polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime a polysilicon gate electrode is also formed above the peripheral circuit region. Spacers are formed on the sidewalls of the polysilicon gate electrode and the bottom electrode. A metal silicide layer is formed over the bottom electrode and the polysilicon gate electrode. A dielectric layer is formed over the metal silicide layer above the bottom electrode. A metallic layer is formed over the dielectric layer to form a capacitor.

摘要翻译： 一种制造电容器的方法。 半导体衬底被分成外围电路区域和存储单元区域。 在存储单元区域中形成隔离结构。 在隔离结构外部的衬底上形成栅氧化层。 在栅极氧化物层和隔离结构上形成多晶硅层。 图案化多晶硅层和栅极氧化物层以在隔离结构上方形成底部电极。 同时，在外围电路区域上方也形成多晶硅栅电极。 隔板形成在多晶硅栅电极和底电极的侧壁上。 在底部电极和多晶硅栅电极上形成金属硅化物层。 在底部电极上方的金属硅化物层上形成介电层。 在电介质层上形成金属层以形成电容器。

公开(公告)号：US06271082B1

公开(公告)日：2001-08-07

申请号：US09557345

申请日：2000-04-25

申请人： Chia-Hsin Hou ,  Jyh-Kuang Lin ,  Tz-Guei Jung ,  Joe Ko

发明人： Chia-Hsin Hou ,  Jyh-Kuang Lin ,  Tz-Guei Jung ,  Joe Ko

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/3212 ,  H01L21/76807 ,  H01L28/55

摘要： A method for fabricating a capacitor is applicable to a fabrication process for a mixed circuit. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.

摘要翻译： 制造电容器的方法适用于混合电路的制造工艺。 该方法包括在具有导电区域的基底上形成第一介电层，停止层和第二介质层。 然后在第二电介质层中形成第一开口，随后在停止层和第一电介质层中形成第二开口，使得第一开口和第二开口形成用于暴露导电区域的双镶嵌开口。 双镶嵌开口填充有第一导电层，以便形成用于连接到导电区域的电容器的通孔塞和下电极。 然后在衬底上形成位于下电极和随后形成的上电极之间的第三电介质层，使得下电极和与下电极相邻的第二电介质层的一部分被第三电介质层完全覆盖 电介质层。 图案化的第二导电层形成在第三介电层的一部分上，由此形成用于完全覆盖下电极的上电极。