公开(公告)号：US20080137570A1

公开(公告)日：2008-06-12

申请号：US11951040

申请日：2007-12-05

申请人： Sang Hyun MIN ,  Tah Joon Park ,  Koon Shik Cho ,  Jae Hyung Lee

发明人： Sang Hyun MIN ,  Tah Joon Park ,  Koon Shik Cho ,  Jae Hyung Lee

IPC分类号： H04B7/00 ,  H04L27/00

CPC分类号： H04L27/3872 ,  H04B1/005 ,  H04B1/707 ,  H04B1/7163 ,  H04B1/71635 ,  H04B1/71637 ,  H04B2201/70705

摘要： There is provided a dual mode WPAN transceiver including a dual mode WPAN transmitter and a dual mode WPAN receiver. In the dual mode WPAN transceiver, the dual mode WPAN transmitter includes a low-speed spreading transmission block spreading low bit-rate data corresponding to a low data rate in low data rate mode, and a high-speed encoding transmission block encoding high bit-rate data corresponding to a high data rate in high data rate mode, and the dual mode WPAN receiver includes an A/D block converting analog I and Q signals into digital I and Q signals, a differential block obtaining a phase difference between the digital I and Q signals from the A/D unit and complex signals adjacent thereto to offset phase errors of the digital I and Q signals, a low-speed despreading reception unit despreading the digital I and Q signals differentiated by the differential block to detect low bit-rate data in low data rate mode, and a high-speed decoding reception unit decoding the digital I and Q signals differentiated by the differential block to detect high bit-rate data.

摘要翻译： 提供了一种双模WPAN收发器，包括双模WPAN发送器和双模WPAN接收器。 在双模WPAN收发器中，双模WPAN发送器包括一个低速扩展传输块，它以低数据速率模式扩展对应于低数据速率的低比特率数据，以及一个高位编码传输块， 速率数据对应于高数据速率模式下的高数据速率，双模WPAN接收机包括将模拟I和Q信号转换成数字I和Q信号的A / D块，差分块获得数字I 和来自A / D单元的Q信号和与其相邻的复信号以消除数字I和Q信号的相位误差;低速解扩接收单元解扩由差分块区分的数字I和Q信号，以检测低位 - 低数据速率模式的速率数据，以及对由差分块区分的数字I和Q信号进行解码以检测高比特率数据的高速解码接收单元。

公开(公告)号：US20080101516A1

公开(公告)日：2008-05-01

申请号：US11925121

申请日：2007-10-26

申请人： Koon Shik Cho ,  Seung Han Ko ,  Jae Hyung Lee ,  Kwang Mook Lee ,  Sang Hyun Min ,  Sang Ho Lee ,  U Sang Lee

发明人： Koon Shik Cho ,  Seung Han Ko ,  Jae Hyung Lee ,  Kwang Mook Lee ,  Sang Hyun Min ,  Sang Ho Lee ,  U Sang Lee

IPC分类号： H04L7/02

CPC分类号： H04L7/08

摘要： Provided is a synchronization device for wireless communication packets, the synchronization device including an A/D (analog/digital) converter that converts an analog input signal applied from outside into a digital signal; a correlation calculating section that is connected to the A/D converter and correlates the converted input signal with a preset reference code so as to calculate a correlation value; a threshold setting section that is connected to the correlation calculating section and sets a threshold value of the correlation value; a maximum correlation detecting section that is connected to the correlation calculating section and the threshold setting section, compares the correlation value with the threshold value, detects the position of the maximum correlation value within each symbol of the input signal when the correlation value is larger than the threshold value, and judges whether a difference in position between the maximum correlation values of consecutive symbols is equal to the period of one symbol or not; a preamble detecting section that is connected to the correlation calculating section and the maximum correlation detecting section and outputs a preamble detection signal when the difference is equal to the period of one symbol; and a data detecting section that receives data of the input signal when the preamble detection signal is applied.

摘要翻译： 提供了一种用于无线通信分组的同步装置，该同步装置包括将从外部施加的模拟输入信号转换为数字信号的A / D（模拟/数字）转换器; 相关计算部分，连接到A / D转换器，并将转换的输入信号与预置的参考码相关联，以便计算相关值; 阈值设定部，与相关计算部连接并设定相关值的阈值; 连接到相关计算部分和阈值设定部分的最大相关检测部分将相关值与阈值进行比较，当相关值大于该值时，检测输入信号的每个符号内的最大相关值的位置 阈值，并且判断连续符号的最大相关值之间的位置差是否等于一个符号的周期; 前同步码检测部，其连接到所述相关计算部和所述最大相关检测部，并且当所述差等于一个符号的周期时，输出前同步码检测信号; 以及数据检测部分，当应用前导码检测信号时，接收输入信号的数据。

公开(公告)号：US08441413B2

公开(公告)日：2013-05-14

申请号：US12827026

申请日：2010-06-30

申请人： Jae Hyung Lee ,  Koon Shik Cho

发明人： Jae Hyung Lee ,  Koon Shik Cho

IPC分类号： G09G5/00

CPC分类号： G09G3/20 ,  G09G3/003 ,  G09G2330/021 ,  H04N13/341 ,  H04N13/398 ,  H04N2213/008

摘要： An apparatus and a system for viewing a 3D image including a synchronization signal receiver for receiving 3D image synchronization signal; a 3D control signal generator for generating left-eye glass control signal and a right-eye glass control signal in accordance with the synchronization signal received; a left-eye glass that opens or intercepts light transmitted to the left-eye glass; a right-eye glass that opens or intercepts light transmitted to the right-eye glass; a central processor that controls operation of the 3D control signal generator and transmits the synchronization signal to the 3D control signal generator; and a power controller that connects or intercepts power supplied to the synchronization signal receiver and the central processor. The power consumption of the apparatus is minimized by supplying power to the synchronization signal receiver and the central processor at a time when the synchronization signal is received and power is intercepted during the rest period.

摘要翻译： 一种用于观看包括用于接收3D图像同步信号的同步信号接收器的3D图像的装置和系统; 用于根据所接收的同步信号产生左眼玻璃控制信号和右眼玻璃控制信号的3D控制信号发生器; 打开或拦截透射到左眼玻璃的光的左眼玻璃; 打开或拦截透射到右眼玻璃的光的右眼玻璃; 控制3D控制信号发生器的操作并将同步信号发送到3D控制信号发生器的中央处理器; 以及功率控制器，其连接或截取提供给同步信号接收器和中央处理器的功率。 在同步信号被接收并且在休息期间被截取电力的时刻，通过向同步信号接收机和中央处理器供电来使设备的功耗最小化。

公开(公告)号：US20130135910A1

公开(公告)日：2013-05-30

申请号：US13591580

申请日：2012-08-22

申请人： Sang Hyun MIN ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

发明人： Sang Hyun MIN ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

IPC分类号： G05F1/70 ,  H02M7/06

CPC分类号： H02M1/4225 ,  H02M2001/0003 ,  Y02B70/126 ,  Y02P80/112

摘要： There are provided a power factor correction apparatus, a direct current/direct current (DC/DC) converter, and a power supplying apparatus, capable of preventing unstable feedback control due to a ripple component by controlling power switching based on a median value between a maximum value and a minimum value of a voltage level of the output power that is received as feedback. The power factor correction apparatus includes a power factor corrector switching input power and correcting a power factor thereof; and a controller detecting a voltage level of power factor-corrected power and controlling the switching of the power factor corrector, based on a median value between a maximum value and a minimum value of the voltage level of the power factor-corrected power detected for a predetermined period of time.

摘要翻译： 提供了功率因数校正装置，直流/直流（DC / DC）转换器和供电装置，其能够通过基于中间值控制功率切换来防止由于纹波分量引起的不稳定的反馈控制 作为反馈接收的输出功率的电压电平的最大值和最小值。 功率因数校正装置包括功率因数校正器切换输入功率并校正其功率因数; 以及控制器，其基于所检测的功率因数校正功率的电压电平的最大值和最小值之间的中值，检测功率因数校正功率的电压电平并控制功率因数校正器的切换， 预定时间段。

公开(公告)号：US07957452B2

公开(公告)日：2011-06-07

申请号：US12098396

申请日：2008-04-04

申请人： Sang Hyun Min ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

发明人： Sang Hyun Min ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

IPC分类号： H04B1/707

CPC分类号： H04B1/707 ,  H04J13/004

摘要： A direct sequence spread spectrum (DSSS) transceiver including a DSSS transmitter and a DSSS receiver, wherein the DSSS transmitter includes: an integral code mapping unit mapping source bit data in one of 2N (N is a natural number) of predetermined symbols by N bits and mapping the symbol in one of integral code words that are obtained by previously integrating each of 2N of bi-orthogonal code words; and a radio frequency (RF) transmitting unit transmitting the integral code words mapped by the integral code mapping unit over an RF carrier wave, and the DSSS receiver includes: an RF receiving unit removing an RF carrier wave from an RF signal from the RF transmitting unit and converting an analog signal obtained by removing the RF carrier wave from the RF signal into a digital signal; a differential circuit unit differentiating and converting the digital signal from the RF receiving unit into bi-orthogonal code words; and a symbol detection unit detecting a symbol corresponding to a maximum value of correlation values between bi-orthogonal code word from the differential circuit unit and a plurality of predetermined reference code words.

摘要翻译： 包括DSSS发射机和DSSS接收机的直接序列扩频（DSSS）收发机，其中DSSS发射机包括：一个整数码映射单元，用于将预定符号的2N（N是自然数）之一的N比特的源比特数据映射到N比特 以及将符号映射到通过预先积分2N个双正交码字中的每一个而获得的积分码字之一中的符号; 以及射频（RF）发送单元，其通过RF载波发送由积分码映射单元映射的积分码字，并且所述DSSS接收机包括：RF接收单元，从RF发射的RF信号中去除RF载波; 将通过从RF信号中去除RF载波而获得的模拟信号转换为数字信号; 差分电路单元，将来自RF接收单元的数字信号分解并转换成双正交码字; 以及符号检测单元，检测与来自差分电路单元的双正交码字和多个预定参考码字之间的相关值的最大值相对应的符号。

公开(公告)号：US20090083571A1

公开(公告)日：2009-03-26

申请号：US12104956

申请日：2008-04-17

申请人： Koon Shik Cho ,  Seung Han Ko ,  Jae Hyung Lee ,  Sang Ho Lee ,  Kwang Mook Lee

发明人： Koon Shik Cho ,  Seung Han Ko ,  Jae Hyung Lee ,  Sang Ho Lee ,  Kwang Mook Lee

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： There are provided a system on chip (SoC) with a low power mode and a method of driving the SoC, the SoC including: a power part supplying a main clock signal and controlling analog and digital power supply at a normal mode and supplying a sub clock signal and turning analog power off at a low power mode; a radio frequency (RF) part generating the main clock signal at the normal mode and stopping operation at the low power mode, under the control of the power part; and a control part operating according to the main clock signal at the normal mode and operating according to the sub clock signal, under to the control of the power part.

摘要翻译： 提供了具有低功率模式的片上系统（SoC）和驱动SoC的方法，SoC包括：提供主时钟信号的电源部分，并以正常模式控制模拟和数字电源，并提供子 时钟信号，并在低功耗模式下关闭模拟电源; 在功率部分的控制下，以正常模式产生主时钟信号并在低功率模式下停止操作的射频（RF）部分; 以及控制部，其在正常模式下根据主时钟信号进行工作，并根据子时钟信号在功率部分的控制下工作。

公开(公告)号：US20090074034A1

公开(公告)日：2009-03-19

申请号：US12098396

申请日：2008-04-04

申请人： Sang Hyun MIN ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

发明人： Sang Hyun MIN ,  Koon Shik Cho ,  Jae Hyung Lee ,  Kwang Mook Lee

IPC分类号： H04B1/707

CPC分类号： H04B1/707 ,  H04J13/004

摘要： A direct sequence spread spectrum (DSSS) transceiver including a DSSS transmitter and a DSSS receiver, wherein the DSSS transmitter includes: an integral code mapping unit mapping source bit data in one of 2N (N is a natural number) of predetermined symbols by N bits and mapping the symbol in one of integral code words that are obtained by previously integrating each of 2N of bi-orthogonal code words; and a radio frequency (RF) transmitting unit transmitting the integral code words mapped by the integral code mapping unit over an RF carrier wave, and the DSSS receiver includes: an RF receiving unit removing an RF carrier wave from an RF signal from the RF transmitting unit and converting an analog signal obtained by removing the RF carrier wave from the RF signal into a digital signal; a differential circuit unit differentiating and converting the digital signal from the RF receiving unit into bi-orthogonal code words; and a symbol detection unit detecting a symbol corresponding to a maximum value of correlation values between bi-orthogonal code word from the differential circuit unit and a plurality of predetermined reference code words.

摘要翻译： 包括DSSS发射机和DSSS接收机的直接序列扩频（DSSS）收发机，其中DSSS发射机包括：一个整数码映射单元，用于将预定符号的2N（N是自然数）之一的N比特的源比特数据映射到N比特 以及将符号映射到通过预先积分2N个双正交码字中的每一个而获得的积分码字之一中的符号; 以及射频（RF）发送单元，其通过RF载波发送由积分码映射单元映射的积分码字，并且所述DSSS接收机包括：RF接收单元，从RF发射的RF信号中去除RF载波; 将通过从RF信号中去除RF载波而获得的模拟信号转换为数字信号; 差分电路单元，将来自RF接收单元的数字信号分解并转换成双正交码字; 以及符号检测单元，检测与来自差分电路单元的双正交码字和多个预定参考码字之间的相关值的最大值相对应的符号。

公开(公告)号：US20100077113A1

公开(公告)日：2010-03-25

申请号：US12262516

申请日：2008-10-31

申请人： Soon Jin CHOI ,  Seung Han Ko ,  Bo II Seo ,  Koon Shik Cho

发明人： Soon Jin CHOI ,  Seung Han Ko ,  Bo II Seo ,  Koon Shik Cho

IPC分类号： G06F3/00

CPC分类号： G06F5/12 ,  G06F2205/126

摘要： Provided is a data communication system including a first-in first-out (FIFO) buffer having a fixed size; a central processing unit (CPU) that writes data stored in a memory into the FIFO buffer; a modem that reads the data written by the CPU from the FIFO buffer; and a modem controller that is connected to the FIFO buffer, the CPU, and the modem, respectively, and controls the CPU such that data having a larger volume than the size of the FIFO buffer can be processed.

摘要翻译： 提供了一种包括具有固定大小的先进先出（FIFO）缓冲器的数据通信系统; 将存储在存储器中的数据写入FIFO缓冲器的中央处理单元（CPU） 调制解调器，从FIFO缓冲器读取CPU写入的数据; 以及分别连接到FIFO缓冲器，CPU和调制解调器的调制解调器控制器，并且控制CPU，使得可以处理具有比FIFO缓冲器的大小更大的数据的数据。

公开(公告)号：US20090022139A1

公开(公告)日：2009-01-22

申请号：US12176129

申请日：2008-07-18

申请人： U Sang Lee ,  Koon Shik Cho

发明人： U Sang Lee ,  Koon Shik Cho

IPC分类号： H04J3/06

CPC分类号： H04L7/042 ,  H04B2001/6912 ,  H04W84/10 ,  H04W84/18 ,  H04W88/04

摘要： There are provided a wireless personal area networks (WPAN) Zigbee receiver and a receiving method thereof that can obtain a spreading gain by a reduction in data rate. A wireless personal area network Zigbee receiver receiving a signal packet including a plurality of functional units having a plurality of symbols, the plurality of functional units each repeated as many as a predetermined extension number according to an aspect of the invention includes: a preamble detection unit detecting a, and generating a preamble synchronization; and an SFD synchronization unit comparing, each symbol of SFD units included in the signal packet with a predetermined SFD reference symbol continuously and repeatedly as many as the extension number, and generating an SFD synchronization signal when each of the symbols of the SFD units is equal to the SFD reference symbol as many as the extension number.

摘要翻译： 提供了可以通过降低数据速率获得扩展增益的无线个人区域网络（WPAN）ZigBee接收机及其接收方法。 根据本发明的一个方面，一种无线个人区域网络ZigBee接收机接收包括具有多个符号的多个功能单元的信号分组，所述多个功能单元每个重复多达预定分机号码，包括：前导码检测单元 检测a并产生前同步码同步; 以及SFD同步单元，将包含在信号分组中的SFD单元的每个符号与预定的SFD参考符号连续且重复地与分机号码一样进行比较，并且当SFD单元的每个符号相等时产生SFD同步信号 到SFD参考符号与分机号码一样多。

公开(公告)号：US20080100391A1

公开(公告)日：2008-05-01

申请号：US11928720

申请日：2007-10-30

申请人： Joon Hyung LIM ,  Tah Joon Park ,  Kwang Mook Lee ,  Koon Shik Cho

发明人： Joon Hyung LIM ,  Tah Joon Park ,  Kwang Mook Lee ,  Koon Shik Cho

IPC分类号： H03K3/02

CPC分类号： H03K3/011 ,  H03L7/06

摘要： There is provided an RC oscillation circuit capable of adjusting an oscillation frequency, and an oscillation method thereof. The RC oscillation circuit including: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

摘要翻译： 提供了能够调节振荡频率的RC振荡电路及其振荡方法。 RC振荡电路包括：包括可变电阻器和可变电容器的RC振荡器，RC振荡器产生具有由可变电阻器的电阻和可变电容器的电容确定的频率的RC振荡信号; 计数对应于RC振荡信号的一个周期的参考振荡信号的时钟数，以产生第一计数值，所述参考振荡信号具有预置频率; 以及频率控制器，通过确定可变电阻器的电阻和可变电容器的电容来控制RC振荡信号的频率，使得第一计数值和预设的第二计数值之间的差小于预设的第一临界值 。