公开(公告)号：US20050238125A1

公开(公告)日：2005-10-27

申请号：US11047255

申请日：2005-01-31

申请人： Jae-Jin Park ,  Seung-Bin You

发明人： Jae-Jin Park ,  Seung-Bin You

IPC分类号： H04B15/00 ,  H03K7/02 ,  H04L25/49

CPC分类号： H04L25/4919

摘要： In a method of interfacing a high-speed signal, a series of digital signals are received from a transmitter in response to a clock signal. The received digital signal is coded based on a K-L level pulse amplitude modulation system in response to the clock signal, wherein K and L are natural numbers and K≠L. The received digital signal is repeatedly coded and the coded digital signal is transferred to a receiver. As a result, crosstalk between adjacent channels may be reduced.

摘要翻译： 在接收高速信号的方法中，响应于时钟信号从发射机接收一系列数字信号。 所接收的数字信号根据时钟信号基于K-L电平脉冲幅度调制系统进行编码，其中K和L是自然数，K

公开(公告)号：US07593468B2

公开(公告)日：2009-09-22

申请号：US11047255

申请日：2005-01-31

申请人： Jae-Jin Park ,  Seung-Bin You

发明人： Jae-Jin Park ,  Seung-Bin You

IPC分类号： H04B14/04

CPC分类号： H04L25/4919

摘要： In a method of interfacing a high-speed signal, a series of digital signals are received from a transmitter in response to a clock signal. The received digital signal is coded based on a K-L level pulse amplitude modulation system in response to the clock signal, wherein K and L are natural numbers and K≠L. The received digital signal is repeatedly coded and the coded digital signal is transferred to a receiver. As a result, crosstalk between adjacent channels may be reduced.

摘要翻译： 在接收高速信号的方法中，响应于时钟信号从发射机接收一系列数字信号。 所接收的数字信号根据时钟信号基于K-L电平脉冲幅度调制系统进行编码，其中K和L是自然数，K

公开(公告)号：US20080088371A1

公开(公告)日：2008-04-17

申请号：US11889419

申请日：2007-08-13

申请人： Seung-Bin You ,  Yong-JIn Cho

发明人： Seung-Bin You ,  Yong-JIn Cho

IPC分类号： H03F3/217

CPC分类号： H03F3/2171

摘要： A digital amplifier, a reference voltage generator for reducing a DC component of an amplified pulse width modulated signal of a digital amplifier, and a method of reducing a DC component of an amplified pulse width modulated signal applied to an input node of a load are described in this disclosure. The digital amplifier includes a pulse width modulation signal generator receiving an input signal and generating an amplified pulse width modulated signal, a filter filtering the amplified pulse width modulated signal and providing the filtered amplified pulse width modulated signal to an input node of a load, and a reference voltage generator providing a reference voltage to a reference node of the load to reduce a DC component of the filtered amplified pulse width modulated signal provided to the input node of the load.

摘要翻译： 描述数字放大器，用于减小数字放大器的放大的脉宽调制信号的DC分量的参考电压发生器以及减小施加到负载的输入节点的经放大的脉宽调制信号的DC分量的方法 在本公开中。 数字放大器包括接收输入信号并产生放大的脉宽调制信号的脉冲宽度调制信号发生器，对经放大的脉宽调制信号进行滤波的滤波器，并将滤波后的放大脉宽调制信号提供给负载的输入节点，以及 参考电压发生器，将参考电压提供给负载的参考节点，以减小提供给负载的输入节点的滤波后的放大脉宽调制信号的直流分量。

公开(公告)号：US20070030061A1

公开(公告)日：2007-02-08

申请号：US11496693

申请日：2006-07-31

申请人： Yong-Jin Cho ,  Seung-Bin You

发明人： Yong-Jin Cho ,  Seung-Bin You

IPC分类号： H03F3/38

CPC分类号： H03F1/305 ,  H03F3/217 ,  H03F2200/331 ,  H03F2200/351 ,  H03F2200/372

摘要： A class D amplifier includes a driver circuit and a reset circuit. The driver circuit is configured to amplify a PWM (pulse width modulation) signal to generate an amplified PWM signal. The reset circuit applies a predetermined voltage at an input of the driver circuit for a time period after a power supply voltage is applied or before the power supply voltage is deactivated, for eliminating pop-up noise.

摘要翻译： D类放大器包括驱动电路和复位电路。 驱动电路被配置为放大PWM（脉宽调制）信号以产生放大的PWM信号。 复位电路在施加电源电压之后或在电源电压被去激活之前的一段时间内在驱动器电路的输入端施加预定电压，以消除弹出噪声。

公开(公告)号：US20110064245A1

公开(公告)日：2011-03-17

申请号：US12850782

申请日：2010-08-05

申请人： Bong-Joo Kim ,  Wang-Seup Yeum ,  Yong-Hee Lee ,  Seung-Bin You ,  Chun Kyun Seok

发明人： Bong-Joo Kim ,  Wang-Seup Yeum ,  Yong-Hee Lee ,  Seung-Bin You ,  Chun Kyun Seok

IPC分类号： H03G3/00 ,  H03F1/00

CPC分类号： H03F3/2173 ,  H03G3/007

摘要： A half-bridge three-level pulse width modulation (PWM) amplifier includes a prescaling unit, a PWM generator configured to convert the input signal to a three-level PWM signal having a first level, a second level and a reference level and an output stage. The prescaling unit scales an input signal according to at least one gain value to provide a scaled signal. The PWM generator varies the width of pulses having the first level and varies the width of pulses having a second level based on the scaled signal. The output stage drives an output node to a level of a first power supply voltage, a second power supply voltage or a third power supply voltage based on the three-level PWM signal. The output node is connected to a load. The magnitude of the at least one gain value compensates for variations of power supply voltages.

摘要翻译： 半桥三电平脉宽调制（PWM）放大器包括一个预分频单元，一个PWM发生器，被配置为将输入信号转换成具有第一电平，第二电平和参考电平的三电平PWM信号，以及输出 阶段。 预分频单元根据至少一个增益值缩放输入信号以提供缩放信号。 PWM发生器改变具有第一电平的脉冲的宽度，并且基于缩放的信号改变具有第二电平的脉冲的宽度。 输出级基于三电平PWM信号将输出节点驱动到第一电源电压，第二电源电压或第三电源电压的电平。 输出节点连接到一个负载。 至少一个增益值的大小补偿电源电压的变化。

公开(公告)号：US20080129377A1

公开(公告)日：2008-06-05

申请号：US11998216

申请日：2007-11-29

申请人： Seung-Bin You ,  Chun-Kyun Seok ,  Yong-Jin Cho

发明人： Seung-Bin You ,  Chun-Kyun Seok ,  Yong-Jin Cho

IPC分类号： H03F3/38 ,  G05F1/44

CPC分类号： G05F1/56 ,  H03F3/38

摘要： A voltage regulator includes a voltage driving circuit and a current sinking unit. The voltage driving circuit is controlled to maintain an output signal at an output node. The current sinking unit is coupled to the output node for generating a sinking current for diverting an external current to the output node. An error amplifier generates a control signal from the output signal and a reference signal. The voltage driving circuit and the current sinking unit are controlled according to such a control signal.

摘要翻译： 电压调节器包括电压驱动电路和电流吸收单元。 控制电压驱动电路以在输出节点处保持输出信号。 电流吸收单元耦合到输出节点，用于产生用于将外部电流转向输出节点的吸收电流。 误差放大器从输出信号和参考信号产生控制信号。 电压驱动电路和电流吸收单元根据这样的控制信号进行控制。

公开(公告)号：US08362832B2

公开(公告)日：2013-01-29

申请号：US12850782

申请日：2010-08-05

申请人： Bong-Joo Kim ,  Wang-Seup Yeum ,  Yong-Hee Lee ,  Seung-Bin You ,  Chun Kyun Seok

发明人： Bong-Joo Kim ,  Wang-Seup Yeum ,  Yong-Hee Lee ,  Seung-Bin You ,  Chun Kyun Seok

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03G3/007

摘要： A half-bridge three-level pulse width modulation (PWM) amplifier includes a prescaling unit, a PWM generator configured to convert the input signal to a three-level PWM signal having a first level, a second level and a reference level and an output stage. The prescaling unit scales an input signal according to at least one gain value to provide a scaled signal. The PWM generator varies the width of pulses having the first level and varies the width of pulses having a second level based on the scaled signal. The output stage drives an output node to a level of a first power supply voltage, a second power supply voltage or a third power supply voltage based on the three-level PWM signal. The output node is connected to a load. The magnitude of the at least one gain value compensates for variations of power supply voltages.

摘要翻译： 半桥三电平脉宽调制（PWM）放大器包括一个预分频单元，一个PWM发生器，被配置为将输入信号转换成具有第一电平，第二电平和参考电平的三电平PWM信号，以及输出 阶段。 预分频单元根据至少一个增益值缩放输入信号以提供缩放信号。 PWM发生器改变具有第一电平的脉冲的宽度，并且基于缩放的信号改变具有第二电平的脉冲的宽度。 输出级基于三电平PWM信号将输出节点驱动到第一电源电压，第二电源电压或第三电源电压的电平。 输出节点连接到一个负载。 至少一个增益值的大小补偿电源电压的变化。

公开(公告)号：US07432759B2

公开(公告)日：2008-10-07

申请号：US11496693

申请日：2006-07-31

申请人： Yong-Jin Cho ,  Seung-Bin You

发明人： Yong-Jin Cho ,  Seung-Bin You

IPC分类号： H03F3/38

CPC分类号： H03F1/305 ,  H03F3/217 ,  H03F2200/331 ,  H03F2200/351 ,  H03F2200/372

摘要： A class D amplifier includes a driver circuit and a reset circuit. The driver circuit is configured to amplify a PWM (pulse width modulation) signal to generate an amplified PWM signal. The reset circuit applies a predetermined voltage at an input of the driver circuit for a time period after a power supply voltage is applied or before the power supply voltage is deactivated, for eliminating pop-up noise.

摘要翻译： D类放大器包括驱动电路和复位电路。 驱动电路被配置为放大PWM（脉宽调制）信号以产生放大的PWM信号。 复位电路在施加电源电压之后或在电源电压被去激活之前的一段时间内在驱动器电路的输入端施加预定电压，以消除弹出噪声。

公开(公告)号：US20060044023A1

公开(公告)日：2006-03-02

申请号：US11134909

申请日：2005-05-23

申请人： Jae-Cheol Yun ,  Seung-Bin You ,  Min-Kyu Song ,  Kyung-June Koh ,  Sang-Kyu Kim

发明人： Jae-Cheol Yun ,  Seung-Bin You ,  Min-Kyu Song ,  Kyung-June Koh ,  Sang-Kyu Kim

IPC分类号： H03K5/22

CPC分类号： H03K5/2481

摘要： An integrated circuit device includes a differential amplifier having first and second input terminals and at least one output terminal. The first input terminal is configured to receive a reference voltage and the second input terminal is configured to receive a time-varying input signal. A normally-on CMOS transmission gate is also provided. The CMOS transmission gate has an input terminal configured to receive a reference voltage and an output terminal electrically coupled to the first input terminal of the differential amplifier. This CMOS transmission gate operates to reduce fluctuations in the reference voltage caused by kick back noise by adding parasitic capacitance to the first input terminal of the differential amplifier.

摘要翻译： 集成电路器件包括具有第一和第二输入端和至少一个输出端的差分放大器。 第一输入端子被配置为接收参考电压，并且第二输入端子被配置为接收时变输入信号。 还提供了通常的CMOS传输门。 CMOS传输门具有被配置为接收参考电压的输入端和电耦合到差分放大器的第一输入端的输出端。 该CMOS传输门通过向差分放大器的第一输入端添加寄生电容来操作以减少由反射噪声引起的参考电压的波动。

公开(公告)号：US20110080217A1

公开(公告)日：2011-04-07

申请号：US12845424

申请日：2010-07-28

申请人： Yong-Hee Lee ,  Chun Kyun Seok ,  Wang-Seup Yeum ,  Seung-Bin You ,  Bong-Joo Kim

发明人： Yong-Hee Lee ,  Chun Kyun Seok ,  Wang-Seup Yeum ,  Seung-Bin You ,  Bong-Joo Kim

IPC分类号： H03F3/04 ,  H03F1/00

CPC分类号： H03F3/181 ,  H03F1/30 ,  H03F3/217

摘要： An audio amplifier includes a compensation unit, an output unit and a calibration unit. The compensation unit generates a compensation signal based on a digital input signal, a digital reference code, a mode signal and a digital approximation code. The output unit generates an output signal based on the compensated input signal. The calibration unit generates the digital approximation code based on the output signal and the mode signal. The digital approximation code includes a plurality of bits that are generated sequentially.

摘要翻译： 音频放大器包括补偿单元，输出单元和校准单元。 补偿单元基于数字输入信号，数字参考码，模式信号和数字近似码产生补偿信号。 输出单元基于经补偿的输入信号产生输出信号。 校准单元基于输出信号和模式信号生成数字近似码。 数字近似码包括顺序生成的多个位。