公开(公告)号：US20120077320A1

公开(公告)日：2012-03-29

申请号：US13238104

申请日：2011-09-21

申请人： Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

发明人： Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

IPC分类号： H01L21/336

CPC分类号： H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

摘要翻译： 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层上方，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

公开(公告)号：US20070241335A1

公开(公告)日：2007-10-18

申请号：US11766655

申请日：2007-06-21

申请人： Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

发明人： Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

IPC分类号： H01L27/108

CPC分类号： H01L27/1108 ,  H01L27/11

摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。

公开(公告)号：US20140199815A1

公开(公告)日：2014-07-17

申请号：US14156781

申请日：2014-01-16

申请人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

发明人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC分类号： H01L29/66

CPC分类号： H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

摘要翻译： 制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘 部分堆叠结构以形成初步阶形状图案结构。 初步阶形形状图案结构具有阶梯形边缘部分。 形成与基板表面接触的柱结构。 部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。 第二开口部分切割下牺牲层的至少边缘部分。

公开(公告)号：US20140197481A1

公开(公告)日：2014-07-17

申请号：US14156607

申请日：2014-01-16

申请人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

发明人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC分类号： H01L29/78

CPC分类号： H01L29/66833 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

摘要： A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

摘要翻译： 垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。 字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。 连接图案将相邻的第一和第二字线的对电连接在同一平面中。 该设备可以是非易失性存储设备或不同类型的设备。

公开(公告)号：US20130309403A1

公开(公告)日：2013-11-21

申请号：US13944479

申请日：2013-07-17

申请人： Jae-Wan PARK ,  You-Min CHA ,  Won-Seok CHO ,  Jae-Mork PARK ,  Jae-Hong AHN ,  Min-Jeong HWANG ,  Tae-Wook KIM ,  Jong-Woo LEE ,  Tae-Seung KIM

发明人： Jae-Wan PARK ,  You-Min CHA ,  Won-Seok CHO ,  Jae-Mork PARK ,  Jae-Hong AHN ,  Min-Jeong HWANG ,  Tae-Wook KIM ,  Jong-Woo LEE ,  Tae-Seung KIM

IPC分类号： C23C14/12

CPC分类号： C23C14/12 ,  B05D1/02 ,  B05D1/60 ,  B05D3/0493 ,  C23C14/243 ,  C23C14/56 ,  H01L51/0008 ,  H01L51/56

摘要： An apparatus for depositing an organic material and a depositing method thereof, wherein a deposition process is performed with respect to a second substrate while transfer and alignment processes are performed with respect to a first substrate in a chamber, so that loss of an organic material wasted in the transfer and alignment processes can be reduced, thereby maximizing material efficiency and minimizing a processing tack time. The apparatus includes a chamber having an interior divided into a first substrate deposition area and a second substrate deposition area, an organic material deposition source transferred to within ones of the first and second substrate deposition areas to spray particles of an organic material onto respective ones of first and second substrates and a first transferring unit to rotate the organic material deposition source in a first direction from one of the first and second substrate deposition areas to an other of the first and second substrate deposition areas.

摘要翻译： 一种用于沉积有机材料的设备及其沉积方法，其中相对于第二衬底执行沉积工艺，同时相对于腔室中的第一衬底进行转移和取向处理，从而浪费有机材料的损失 可以减少转移和对准过程，从而最大化材料效率并最小化处理粘着时间。 该装置包括具有分为第一衬底沉积区域和第二衬底沉积区域的内部的腔室，被转移到第一和第二衬底沉积区域内的有机材料沉积源，以将有机材料的颗粒喷射到 第一和第二基板和第一转印单元，用于使有机材料沉积源沿第一方向从第一和第二基板沉积区域之一旋转到第一和第二基板沉积区域中的另一个。

公开(公告)号：US20100279021A1

公开(公告)日：2010-11-04

申请号：US12762721

申请日：2010-04-19

申请人： Jae-Wan PARK ,  You-Min CHA ,  Won-Seok CHO ,  Jae-Mork PARK ,  Jae-Hong AHN ,  Min-Jeong HWANG ,  Tae-Wook KIM ,  Jong-Woo LEE ,  Tae-Seung KIM

发明人： Jae-Wan PARK ,  You-Min CHA ,  Won-Seok CHO ,  Jae-Mork PARK ,  Jae-Hong AHN ,  Min-Jeong HWANG ,  Tae-Wook KIM ,  Jong-Woo LEE ,  Tae-Seung KIM

IPC分类号： B05D1/02 ,  B05C5/00

CPC分类号： C23C14/12 ,  B05D1/02 ,  B05D1/60 ,  B05D3/0493 ,  C23C14/243 ,  C23C14/56 ,  H01L51/0008 ,  H01L51/56

摘要： An apparatus for depositing an organic material and a depositing method thereof, wherein a deposition process is performed with respect to a second substrate while transfer and alignment processes are performed with respect to a first substrate in a chamber, so that loss of an organic material wasted in the transfer and alignment processes can be reduced, thereby maximizing material efficiency and minimizing a processing tack time. The apparatus includes a chamber having an interior divided into a first substrate deposition area and a second substrate deposition area, an organic material deposition source transferred to within ones of the first and second substrate deposition areas to spray particles of an organic material onto respective ones of first and second substrates and a first transferring unit to rotate the organic material deposition source in a first direction from one of the first and second substrate deposition areas to an other of the first and second substrate deposition areas.

摘要翻译： 一种用于沉积有机材料的设备及其沉积方法，其中相对于第二衬底执行沉积工艺，同时相对于腔室中的第一衬底进行转移和取向处理，从而浪费有机材料的损失 可以减少转移和对准过程，从而最大化材料效率并最小化处理粘着时间。 该装置包括具有分为第一衬底沉积区域和第二衬底沉积区域的内部的腔室，被转移到第一和第二衬底沉积区域内的有机材料沉积源，以将有机材料的颗粒喷射到 第一和第二基板和第一转印单元，用于使有机材料沉积源沿第一方向从第一和第二基板沉积区域之一旋转到第一和第二基板沉积区域中的另一个。