公开(公告)号：US20120077320A1

公开(公告)日：2012-03-29

申请号：US13238104

申请日：2011-09-21

申请人： Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

发明人： Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

IPC分类号： H01L21/336

CPC分类号： H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

摘要翻译： 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层上方，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

公开(公告)号：US20120098048A1

公开(公告)日：2012-04-26

申请号：US13221380

申请日：2011-08-30

申请人： Byeong-In CHOE ,  Jae-Hoon JANG ,  Sun-Il SHIM ,  Han-Soo KIM ,  Jin-Man HAN

发明人： Byeong-In CHOE ,  Jae-Hoon JANG ,  Sun-Il SHIM ,  Han-Soo KIM ,  Jin-Man HAN

IPC分类号： H01L29/792 ,  H01L21/20

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线和字符串选择线（SSL）。 通道沿基本上垂直于基板的顶表面的第一方向延伸，并且通道的厚度根据高度而不同。 GSL，字线和SSL顺序地形成在通道的第一方向的侧壁上并且彼此间隔开。

公开(公告)号：US20140199815A1

公开(公告)日：2014-07-17

申请号：US14156781

申请日：2014-01-16

申请人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

发明人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC分类号： H01L29/66

CPC分类号： H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

摘要翻译： 制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘 部分堆叠结构以形成初步阶形状图案结构。 初步阶形形状图案结构具有阶梯形边缘部分。 形成与基板表面接触的柱结构。 部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。 第二开口部分切割下牺牲层的至少边缘部分。

公开(公告)号：US20140197481A1

公开(公告)日：2014-07-17

申请号：US14156607

申请日：2014-01-16

申请人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

发明人： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC分类号： H01L29/78

CPC分类号： H01L29/66833 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

摘要： A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

摘要翻译： 垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。 字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。 连接图案将相邻的第一和第二字线的对电连接在同一平面中。 该设备可以是非易失性存储设备或不同类型的设备。

公开(公告)号：US20100012997A1

公开(公告)日：2010-01-21

申请号：US12499980

申请日：2009-07-09

申请人： Young-Chul JANG ,  Han-Soo KIM ,  Jae-Hun JEONG ,  Soon-Moon JUNG

发明人： Young-Chul JANG ,  Han-Soo KIM ,  Jae-Hun JEONG ,  Soon-Moon JUNG

IPC分类号： H01L29/788

CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049

摘要： Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

摘要翻译： 公开了闪存装置和操作方法。 闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。 底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。 顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。 井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到 顶好

公开(公告)号：US20090294821A1

公开(公告)日：2009-12-03

申请号：US12473055

申请日：2009-05-27

申请人： Jong-In YUN ,  Soon-Moon JUNG ,  Han-Soo KIM ,  Hoo-Sung CHO ,  Jun-Beom PARK ,  Jae-Hun JEONG

发明人： Jong-In YUN ,  Soon-Moon JUNG ,  Han-Soo KIM ,  Hoo-Sung CHO ,  Jun-Beom PARK ,  Jae-Hun JEONG

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.

摘要翻译： 本文示例性描述的一个实施方案通常可以表征为半导体器件，其包括位于半导体衬底上方的较低级器件层，位于下级器件层上的层间绝缘膜和位于层间绝缘膜上方的上位器件层。 下层器件层可以包括形成在衬底中的多个器件。 上级器件层可以包括多个半导体图案和形成在多个半导体图案中的每一个中的至少一个器件。 多个半导体图案可以彼此电隔离。 多个半导体图案中的每一个可以包括至少一个有效部分和至少一个电连接到该至少一个有效部分的主体接触部分。

公开(公告)号：US20080075013A1

公开(公告)日：2008-03-27

申请号：US11862902

申请日：2007-09-27

申请人： Han-Soo KIM

发明人： Han-Soo KIM

IPC分类号： H04L12/26

CPC分类号： H04L41/06 ,  H04L43/0811 ,  H04L69/40 ,  H04W80/06 ,  H04W80/10

摘要： An apparatus and method for connection failure control in an Unlicensed Mobile Access (UMA) network is provided, which includes while providing a current service, determining whether a base station periodically receives a message to determine a lower layer connection status to determine the lower layer connection status, continuously providing the current service if the base station does not receive the message periodically, transmitting a message to inform a connection failure of the lower layer, if the mobile station does not receive the message to inform the connection failure, continuously providing the current service, and if the mobile station receives the message to inform the connection failure, performing a connection failure management process.

摘要翻译： 提供了一种用于非授权移动接入（UMA）网络中的连接失败控制的装置和方法，其包括在提供当前服务的同时确定基站周期性地接收消息以确定较低层连接状态以确定较低层连接 状态，如果基站周期性地不接收消息，则连续提供当前业务，如果移动台没有接收到消息以通知连接失败，则发送消息以通知下层的连接故障，连续提供当前的 服务，并且如果移动站接收到消息以通知连接失败，则执行连接失败管理过程。