公开(公告)号：US06214661B1

公开(公告)日：2001-04-10

申请号：US09489771

申请日：2000-01-21

Applicant: Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

Inventor： Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

IPC: H01L218242

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L28/55

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: a) preparing a bottom Pt electrode formation; b) subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; c) depositing a BSTO layer on said oxygen enriched Pt layer; d) depositing an upper Pt electrode layer on the BSTO layer; e) subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and f) depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract translation: 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止BSTO材料层的氧扩散，包括：a）制备底部Pt电极 b）使底Pt层电极形成氧气等离子体处理，在底Pt电极上形成富氧Pt层; c）在所述富氧Pt层上沉积BSTO层; d）将上Pt电极层沉积在 BSTO层; e）使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 以及）在配有氧的Pt层上部Pt上沉积Pt层。

公开(公告)号：US5701268A

公开(公告)日：1997-12-23

申请号：US701892

申请日：1996-08-23

Applicant: Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

Inventor： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

CPC classification number: G11C7/06 ,  G11C11/4091

Abstract: Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) towards the first potential, prior to amplification of the difference in potential between the first and second sense bit signal lines by the sense amplifier. The present invention enables the sense amplifier to operate in an environment where the power supply voltage (e.g., VCC) is reduced and the different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) to be amplified are initially established at potentials below the normal sensitivity of the sense amplifier.

Abstract translation: 集成电路存储器件包括电耦合到读出放大器的相应第一和第二感测位信号线的至少第一和第二存储器单元。 感测放大器包括用于通过将这些线驱动到相应的第一和第二不同电位来放大第一和第二感测位信号线之间的电位差的电路。 还提供驱动电路，用于响应于施加升压控制信号，同时将第一和第二感测位信号线驱动朝向第一电位。 该驱动电路优选地包括串联电连接在升压控制输入和第一感测位信号线之间的第一电容器和串联电连接在升压控制输入和第二感测位信号线之间的第二电容器。 升压控制信号被建立在第一电位，以驱动来自不同中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E，fra 1/2 + EE VCC）的感测位信号线朝着第一 在由感测放大器放大第一和第二感测位信号线之间的电位差之前的电位。 本发明使得读出放大器能够在电源电压（例如，VCC）减小的环境中工作，并且不同的中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E， + EE VCC）最初建立在低于读出放大器正常灵敏度的电位。

公开(公告)号：US06441422B1

公开(公告)日：2002-08-27

申请号：US09706482

申请日：2000-11-03

Applicant: Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Jai-hoon Sim

Inventor： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Jai-hoon Sim

IPC: H01L27108

CPC classification number: H01L27/10864 ,  H01L27/10867

Abstract: An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.

Abstract translation: 提供具有低结漏电的超可扩展混合存储器单元及其制造工艺。 超可扩展混合存储器单元包含与身体区域的导电连接，从而避免由于掩埋带外扩散区域而导致的P阱的隔离。 超可扩展混合存储器单元通过使用允许P阱保持连接到存储器单元的主体的比普通隔离区更浅的方式来避免上述情况。

公开(公告)号：US5686735A

公开(公告)日：1997-11-11

申请号：US390357

申请日：1995-02-17

Applicant: Jai-hoon Sim

Inventor： Jai-hoon Sim

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78654

Abstract: An SOI transistor whose source region and/or drain region have a heterostructure made up of at least two different semiconductor materials, to thereby prevent a bipolar-induced breakdown.

Abstract translation: SOI晶体管，其源极区和/或漏极区具有由至少两个不同的半导体材料构成的异质结构，从而防止双相诱发击穿。