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公开(公告)号：US07257247B2
公开(公告)日：2007-08-14
申请号：US09683836
申请日：2002-02-21
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译： 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定给定掩模层上的缺陷何时发生。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
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公开(公告)号：US07492940B2
公开(公告)日：2009-02-17
申请号：US11761856
申请日：2007-06-12
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译： 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定何时发生了给定掩模层上的缺陷。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
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公开(公告)号：US07492941B2
公开(公告)日：2009-02-17
申请号：US11769431
申请日：2007-06-27
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
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4.发明授权公开(公告)号：US06539321B2
公开(公告)日：2003-03-25
申请号：US09906919
申请日：2001-07-17
IPC分类号： G06F1900
CPC分类号： G03F7/70508 , G03F7/70516 , G03F7/70608 , G03F7/70625
摘要： Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.
摘要翻译： 用于对用于电子封装的衬底或半导体器件上的印刷或集成电路中遇到的形貌诱导线宽变化的边缘偏置校正的方法。 该方法修改了基于先前水平数据和模型的当前水平的数据，关于形貌将影响抗蚀剂和/或抗反射涂层（ARC）厚度的方式，以便改进线宽（LW）控制， 一般来说，赋予改进的处理窗口。 该方法可以以存储在计算机可用介质上的一个或多个程序模块中体现的计算机可执行指令的形式来实现。
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公开(公告)号：US06395438B1
公开(公告)日：2002-05-28
申请号：US09756540
申请日：2001-01-08
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F1/80 , G03F7/70433
摘要： A method for including etch bias corrections in pre-processing of integrated circuit design data to compensate for deviations introduced during lithographic printing and etching. The design data is segmented, and etch bias corrections are applied to the segments based on their proximity to adjacent design features. Adjusted or corrected design data is produced which may be used to create a mask which includes etch bias corrections for better fidelity and reproduction of the original design in the etching step. Etch bias corrections may also be applied based upon characteristics of regions defined in the design, or on a pattern density of the design.
摘要翻译： 一种在集成电路设计数据的预处理中包括蚀刻偏差校正以补偿在平版印刷和蚀刻期间引入的偏差的方法。 设计数据被分段，并且基于它们与相邻设计特征的接近度，将蚀刻偏差校正应用于段。 产生调整或校正的设计数据，其可用于创建掩模，该掩模包括用于在蚀刻步骤中更好保真度和再现原始设计的蚀刻偏差校正。 也可以基于设计中定义的区域的特征或设计的图案密度来应用蚀刻偏差校正。
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公开(公告)号：US06704695B1
公开(公告)日：2004-03-09
申请号：US09354879
申请日：1999-07-16
IPC分类号： G06G748
CPC分类号： G03F1/36
摘要： A method and structure for creating a photomask data set includes inputting a design data set, creating a simulated printed data set by applying a lithography simulation model to chosen levels of the design data set, merging each chosen level of the design data set with each corresponding level of the simulated printed data set in order to produce a merged design data set, applying at least one test to the merged design data set, correcting the design data set based on results of the test to produce a corrected design data set, repeating the creating of the simulated printed data, merging, applying the test and correcting using the corrected design data set until the corrected design data set passes the test, and outputting the corrected design data set as the photomask data set.
摘要翻译： 一种用于创建光掩模数据集的方法和结构，包括输入设计数据集，通过将光刻仿真模型应用于设计数据集的选定级别来创建模拟印刷数据集，将每个选定级别的设计数据集与每个相应的 水平的模拟印刷数据集合，以便产生合并的设计数据集，对合并的设计数据集应用至少一个测试，基于测试结果校正设计数据集，以产生校正的设计数据集，重复 创建模拟打印数据，合并，应用测试并使用校正后的设计数据集进行校正，直到校正后的设计数据集通过测试，并输出校正后的设计数据集作为光掩模数据集。
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公开(公告)号：US06667136B2
公开(公告)日：2003-12-23
申请号：US10200912
申请日：2002-07-22
IPC分类号： G03F900
摘要： A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.
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8.发明授权Error checking of simulated printed images with process window effects included 有权对包含过程窗口效应的模拟打印图像进行错误检查公开(公告)号：US06373975B1
公开(公告)日：2002-04-16
申请号：US09237148
申请日：1999-01-25
IPC分类号： G06K900
CPC分类号： G06T7/0006 , G03F1/36 , G06T2207/30148
摘要： A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.
摘要翻译： 用于检查用于设计规则违规的半导体设计的结构和方法包括基于半导体设计产生预测的印刷结构（即，理想图像），改变理想图像以包括潜在的制造变化，由此产生至少两个代表不同的生产图像 制造质量，并将生产图像与设计规则进行比较以产生错误列表。
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公开(公告)号：US06458493B2
公开(公告)日：2002-10-01
申请号：US09325945
申请日：1999-06-04
IPC分类号： G03F900
摘要： A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.
摘要翻译： 一种光掩模的方法和结构，其包括具有第一透射率的衬底，要转印到感光层的第一图案（具有低于第一透射率的第二透射率的第一图案）和具有第三透射率的第二图案 第二透射率和小于第一透射率。 第二图案与第一图案的至少一部分相邻，并且基板和第二图案基本上同相地发射光。
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公开(公告)号：US06429469B1
公开(公告)日：2002-08-06
申请号：US09705031
申请日：2000-11-02
申请人： Archibald J. Allen , Orest Bula , John M. Cohn , Daniel Cole , Edward W. Conrad , William C. Leipold
发明人： Archibald J. Allen , Orest Bula , John M. Cohn , Daniel Cole , Edward W. Conrad , William C. Leipold
IPC分类号： H01L2710
CPC分类号： H01L27/0629
摘要： A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.
摘要翻译： 一种用于半导体芯片的结构，其包括具有用于存储和处理数据的第一单元的第一区域，以及具有OPC结构的第一区域之外的第二区域，其中OPC结构包括去耦电容器。 第一单元的有源栅极的线宽与OPC结构尺寸相同或相似。 OPC结构减少了第一单元中的有源器件的邻近效应，并且包括位于第二区域中的N型FET和P型FET。 OPC结构可以具有大于第一单元的宽度。 第二区域可以是多个OPC结构，由此第二区域包括多个去耦电容器。 第一单元中的有源器件被隔开第一距离，并且OPC结构与有源器件分开第一距离。
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