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1.发明授权公开(公告)号：US06973541B1
公开(公告)日：2005-12-06
申请号：US10255495
申请日：2002-09-26
申请人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Kelvin S. Vartti , Stephen Sutter , Chad M. Sonmore
发明人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Kelvin S. Vartti , Stephen Sutter , Chad M. Sonmore
CPC分类号： G06F9/30047 , G06F12/08 , G06F12/0891
摘要： An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a “page zero” instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, the IP issues one or more page zero requests using a background interface of the IP. In one embodiment, each request results in the initialization of a page of memory. While page zero requests are issued over the background interface, the IP may continue issuing other read and write requests to memory over a primary interface of the IP.
摘要翻译： 提供了一种用于在数据处理系统中初始化存储器的改进的系统和方法。 根据本发明的一个方面，提供了可以由指令处理器执行以启动存储器初始化的“页零”指令。 在执行指令时，IP使用IP的后台接口发出一个或多个页面零请求。 在一个实施例中，每个请求导致一页存储器的初始化。 当通过后台接口发出页面零请求时，IP可以通过IP的主接口继续向存储器发出其他读取和写入请求。
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公开(公告)号：US07254657B1
公开(公告)日：2007-08-07
申请号：US11118051
申请日：2005-04-29
IPC分类号： G06F1/00
CPC分类号： G06F13/4217
摘要： A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller coupled to the bus. The system bus implements one of a first and a second system bus protocols. The interface unit is compatible with the first system bus protocol in a first selectable mode and the second system bus protocol in a second selectable mode, and the controller is compatible with one of the system bus protocols. A mode register is coupled to the interface unit, and the interface unit selects the first mode responsive to a first value of the mode register and selects the second mode responsive to a second value of the mode register. A scan controller is coupled to the mode register for scanning a value into the mode register.
摘要翻译： 具有模式可选总线接口的计算系统。 在一个实施例中，计算系统包括系统总线，经由接口单元耦合到总线的处理器和耦合到总线的控制器。 系统总线实现第一和第二系统总线协议之一。 接口单元在第一可选模式下与第一系统总线协议兼容，第二系统总线协议以第二可选模式兼容，并且控制器与系统总线协议之一兼容。 模式寄存器耦合到接口单元，并且接口单元响应于模式寄存器的第一值来选择第一模式，并且响应于模式寄存器的第二值选择第二模式。 扫描控制器耦合到模式寄存器，用于将值扫描到模式寄存器中。
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公开(公告)号：US20100302042A1
公开(公告)日：2010-12-02
申请号：US12790259
申请日：2010-05-28
申请人： David Barnett , Brian O'Dell , Stephen Sutter
发明人： David Barnett , Brian O'Dell , Stephen Sutter
IPC分类号： G08B23/00
摘要： A computing system helps a person live independently by providing reminders, alerts, and alarms of situations that require the person's attention, notifying another party for emergency or other advice or assistance as necessary. The system receives data from a variety of sensors around the person's environment, developing one or more meaningful composite virtual sensor signals as a function of the data from the physical sensors. Rules operate as a function of the virtual sensor signals to notify the user and/or another party of the situation by way of a smartphone application, cell phone text message, PDA, or other device.
摘要翻译： 计算机系统通过提供需要人员注意的情况的提醒，警报和警报来帮助个人独立生活，并在必要时向另一方通知紧急情况或其他建议或协助。 该系统从人的环境周围的各种传感器接收数据，根据物理传感器的数据开发一个或多个有意义的复合虚拟传感器信号。 规则作为虚拟传感器信号的函数来操作，以通过智能电话应用，手机短信，PDA或其他设备通知用户和/或另一方的情况。
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4.发明授权System and method for selectively storing bus information associated with memory coherency operations 有权用于选择性地存储与存储器一致性操作相关联的总线信息的系统和方法公开(公告)号：US07356652B1
公开(公告)日：2008-04-08
申请号：US11390680
申请日：2006-03-28
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F11/349 , G06F11/364 , G06F2201/82 , G06F2201/885
摘要： A manner for judiciously snooping or otherwise monitoring bus operations associated with maintaining cache or other memory coherency in a computing system. A bus snoop information storage mode is established that identifies information pertaining to the bus snoop operations used to maintain memory coherency. The bus snoop information storage mode is selectable, relative to possible other modes. When the bus snoop information storage mode is activated, the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles is disregarded, while the current state of the information pertaining to the bus snoop operations upon completion of the bus snoop operations is stored.
摘要翻译： 用于明智地窥探或以其他方式监视与在计算系统中保持高速缓存或其他存储器一致性相关联的总线操作的方式。 建立了总线窥探信息存储模式，其识别与用于维持内存一致性的总线侦听操作有关的信息。 相对于可能的其他模式，可选择总线侦听信息存储模式。 当总线侦听信息存储模式被激活时，不考虑与总线侦听停止周期有关的总线侦听操作的信息，而总线侦听操作完成时与总线侦听操作有关的信息的当前状态是 存储。
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公开(公告)号：US5842038A
公开(公告)日：1998-11-24
申请号：US728332
申请日：1996-10-10
CPC分类号： G06F13/1642
摘要： A system and method for transmitting commands from one or more input/output devices to a memory is provided. An identification tag is appended to each command to define the command as either a read or write command. The read commands are separated from the write commands based on the state of the identification tag, and the read and write commands are separately queued. The read commands are stored in a first command queue, and the write commands are stored in a second, separate, command queue. The read commands in the first command queue are successively transferred to the memory upon completion of the current memory read function, and the write commands in the second command queue are successively transferred to the memory upon completion of the current memory write function. The transfer of the read and write commands is independent.
摘要翻译： 提供了一种用于将命令从一个或多个输入/输出设备传送到存储器的系统和方法。 每个命令附加一个识别标签，将该命令定义为读取或写入命令。 读取命令根据识别标签的状态与写入命令分开，读取和写入命令分别排队。 读取命令存储在第一个命令队列中，写入命令存储在第二个独立的命令队列中。 完成当前存储器读取功能后，第一命令队列中的读取命令被连续地传送到存储器，并且当完成当前存储器写入功能时，第二命令队列中的写入命令被连续传送到存储器。 读取和写入命令的传输是独立的。
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公开(公告)号：US5867731A
公开(公告)日：1999-02-02
申请号：US695618
申请日：1996-08-12
申请人： David P. Williams , Stephen Sutter
发明人： David P. Williams , Stephen Sutter
CPC分类号： H04L12/46
摘要： A system for use in transferring data packets across different clock domains using an input data register for receiving a block of data packets with the input data register and a plurality of interface registers located in the first clock domain for transferring a block of data packets from the input register to a second clock domain in response to a request signal with the system prioritizing the transfer of multiple data packets within the block of data packets by length in order to transfer the longer word packets first and the shorter word packets last with the shortest word packets within the block bundled together and simultaneously transferring across an asynchronous interface.
摘要翻译： 一种用于使用输入数据寄存器在不同时钟域传输数据分组的系统，所述输入数据寄存器用于接收具有输入数据寄存器的数据分组块，以及位于第一时钟域中的多个接口寄存器，用于从 输入寄存器到第二时钟域，响应于请求信号，其中系统对数据分组块内的多个数据分组的传输进行优先级排序，以便首先传送较长的单词分组，并且用最短的单词传送较短的单词分组 块内的数据包捆绑在一起，同时跨异步接口传输。
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7.发明授权Processor command for prompting a storage controller to write a day clock value to specified memory location 失效处理器命令，用于提示存储控制器将日期时钟值写入指定的存储位置
公开(公告)号：US5809540A
公开(公告)日：1998-09-15
申请号：US577909
申请日：1995-12-04
CPC分类号： G06F11/3466 , G06F1/14 , G06F2201/835
摘要： A method and apparatus for efficiently reading a day clock and storing the value into main storage. An advantage is that the memory storage command can request the main storage control to read a current day clock value and store the value into a main storage location specified by the requesting processor while allowing the requesting processor to continue processing other commands. A further advantage is that the requesting processor does not have to wait for the return of a day clock value or the generation of a main storage write request which may reduce the number of main storage I/O bus requests and bus transfer cycles over that normally required to transfer the day clock value to the requesting processor and then back to main storage.
摘要翻译： 一种用于有效读取日间时钟并将该值存储到主存储器中的方法和装置。 优点是，存储器存储命令可以请求主存储控制器读取当前日期时钟值，并将该值存储到由请求处理器指定的主存储位置中，同时允许请求处理器继续处理其他命令。 另一个优点是，请求处理器不必等待日时钟值的返回或主存储写请求的产生，这可以减少主存储I / O总线请求的数量和总线传输周期的数量 将日间时钟值传送到请求处理器，然后返回到主存储器。
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