公开(公告)号：US20080017857A1

公开(公告)日：2008-01-24

申请号：US11859890

申请日：2007-09-24

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

IPC分类号： H01L23/58

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US20070160920A1

公开(公告)日：2007-07-12

申请号：US11687731

申请日：2007-03-19

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

IPC分类号： G03F1/00 ,  G03C5/00 ,  G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US20060225023A1

公开(公告)日：2006-10-05

申请号：US10907494

申请日：2005-04-04

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US20060026472A1

公开(公告)日：2006-02-02

申请号：US10710642

申请日：2004-07-27

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

IPC分类号： G06F17/50 ,  G01R31/28

CPC分类号： G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

公开(公告)号：US20060170104A1

公开(公告)日：2006-08-03

申请号：US11277663

申请日：2006-03-28

申请人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

发明人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

IPC分类号： H01L23/52

CPC分类号： G01R31/2884 ,  G01R31/307 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.

摘要翻译： 用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。 第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每个中的第二线 对最初与第一金属互连级别下方的导电结构电隔离。 第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

公开(公告)号：US20050282297A1

公开(公告)日：2005-12-22

申请号：US10710114

申请日：2004-06-18

申请人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

发明人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

IPC分类号： G01R31/28 ,  G01R31/307 ,  H01L21/00 ,  H01L23/544

CPC分类号： G01R31/2884 ,  G01R31/307 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.

摘要翻译： 用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。 第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每一个中的第二线 对最初与第一金属互连级别下方的导电结构电隔离。 第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

公开(公告)号：US20060066342A1

公开(公告)日：2006-03-30

申请号：US11280008

申请日：2005-11-16

申请人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

发明人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

IPC分类号： G01R31/26

CPC分类号： G01R31/31727 ,  G01R31/025 ,  G01R31/30 ,  G01R31/31725

摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

公开(公告)号：US20070108964A1

公开(公告)日：2007-05-17

申请号：US11382601

申请日：2006-05-10

申请人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

发明人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

IPC分类号： G01R31/28

CPC分类号： G01R31/31727 ,  G01R31/025 ,  G01R31/30 ,  G01R31/31725

摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

摘要翻译： 公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。 屏蔽与时钟信号接线相邻，接地线将屏蔽接地。 屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。 本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

公开(公告)号：US20050285611A1

公开(公告)日：2005-12-29

申请号：US10710222

申请日：2004-06-28

申请人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

发明人： John Cohn ,  Leah Pastel ,  Thomas Sopchak ,  David Vallett

IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R31/30 ,  G01R31/317

CPC分类号： G01R31/31727 ,  G01R31/025 ,  G01R31/30 ,  G01R31/31725

摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

摘要翻译： 公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。 屏蔽与时钟信号接线相邻，接地线将屏蔽接地。 屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。 本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

公开(公告)号：US20060022671A1

公开(公告)日：2006-02-02

申请号：US10710683

申请日：2004-07-28

申请人： Theodore Levin ,  David Vallett

发明人： Theodore Levin ,  David Vallett

IPC分类号： G01R33/02

CPC分类号： G01R31/2886 ,  G01R15/20 ,  G01R31/3004 ,  G01R31/3025

摘要： An apparatus and a method for testing semiconductor devices, such as individual integrated circuits in semiconductor chips, by directing a current in each circuit through a respective selected predetermined path to establish, in each circuit, a respective focused magnetic field and converting each such magnetic field into a respective voltage which, when fed to respective amplifier gated with a respective selected frequency, will modulate each such respective voltage. Each such respective voltage is then used to create a respective pulsating magnetic field that when detected by a respective remote magnetic sensor will provide a series of respective signals representative of the current in the respective circuit from which the pulsating magnetic field was derived. By applying each such series of voltages to a lock-in amplifier synchronized at the respective frequencies gating each respective amplifier the current in each circuit being tested can be accurately determined and will be free of errors due to circuit noise or crosstalk between the circuits under test.

摘要翻译： 一种用于测试半导体芯片中的各个集成电路的半导体器件的装置和方法，通过在每个电路中引导电流通过相应的选定的预定路径，以在每个电路中建立相应的聚焦磁场并将每个这样的磁场 当被馈送到以相应选定频率门控的相应放大器时，将调制每个这样的相应电压。 然后使用每个这样的各个电压来产生相应的脉动磁场，当相应的远程磁传感器检测到时，将提供一系列相应的信号，该信号表示从其产生脉动磁场的相应电路中的电流。 通过将每个这样的一系列电压施加到锁定放大器，该锁定放大器在各自的频率上同步，门控各个放大器，可以精确地确定正在测试的每个电路中的电流，并且将由于被测电路之间的电路噪声或串扰而没有错误 。