公开(公告)号：US20080017857A1

公开(公告)日：2008-01-24

申请号：US11859890

申请日：2007-09-24

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

IPC分类号： H01L23/58

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US20070160920A1

公开(公告)日：2007-07-12

申请号：US11687731

申请日：2007-03-19

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

IPC分类号： G03F1/00 ,  G03C5/00 ,  G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US20060225023A1

公开(公告)日：2006-10-05

申请号：US10907494

申请日：2005-04-04

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US20060026472A1

公开(公告)日：2006-02-02

申请号：US10710642

申请日：2004-07-27

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

IPC分类号： G06F17/50 ,  G01R31/28

CPC分类号： G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

公开(公告)号：US20060022693A1

公开(公告)日：2006-02-02

申请号：US10710640

申请日：2004-07-27

申请人： Greg Bazan ,  John Cohn ,  Matthew Grady ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak

发明人： Greg Bazan ,  John Cohn ,  Matthew Grady ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  G01R31/31855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.

摘要翻译： 用于监测集成电路芯片中的缺陷的电路和方法。 所述电路包括缺陷监测部分和感测元件部分，所述缺陷监测部分耦合到布置在链中的感测元件的输入或耦合在感测元件和链的形成部分之间。

公开(公告)号：US20050172187A1

公开(公告)日：2005-08-04

申请号：US11093356

申请日：2005-03-30

申请人： Frank Angelotti ,  Louis Bushard ,  Matthew Grady ,  Scott Strissel

发明人： Frank Angelotti ,  Louis Bushard ,  Matthew Grady ,  Scott Strissel

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318577

摘要： A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.

摘要翻译： 一种测试装置和方法，用于通过在所述触点的子集中提供将每个相应的各个测试触点耦合到选择的接口来测试用于交流（AC）缺陷的集成电路的数据存储装置的输入/输出信号引脚 多个数据存储输入/输出信号引脚，使得当选择的数据串被引入到集成电路中，使得集成电路中的数据存储设备上的每个输入/输出引脚将被依次测试，从而所需的触点数量 由测试仪可以减少。

公开(公告)号：US20050049810A1

公开(公告)日：2005-03-03

申请号：US10604887

申请日：2003-08-25

申请人： Tange Barbour ,  Thomas Barnett ,  Matthew Grady ,  William Huott ,  Michael Ouellette

发明人： Tange Barbour ,  Thomas Barnett ,  Matthew Grady ,  William Huott ,  Michael Ouellette

IPC分类号： G06F19/00 ,  G11C29/44

CPC分类号： G11C29/44 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/4402

摘要： A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.

摘要翻译： 一种用于在集成电路器件上确定最小后期制作测试时间以实现利用缺陷计数的该器件的最佳可靠性的方法和系统。 对集成电路装置上的缺陷单元或缺陷单元（DEFECTS）的有缺陷单元的数量进行计数，该计数作为确定最小测试时间的基础。 更高数量的缺陷导致更长的后期测试，以实现集成电路器件的最佳可靠性。 DEFECTS的数量可以在集成电路设备内部的设备上进行计数，并可用于确定最低要求的测试时间。 还可以通过拦截路由到另一设备的信息，在集成电路设备外部获得缺陷数量。 内部和外部提供的信息还可以显示缺陷的物理位置，以进一步完善最低要求的测试时间。