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公开(公告)号：US08332598B2
公开(公告)日：2012-12-11
申请号：US11159741
申请日：2005-06-23
IPC分类号： G06F12/00
CPC分类号： G06F13/1626 , G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic, a reorder table and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The reorder table includes two or more table elements. Each table element includes a shared address component and an independent address component corresponding to each of the two or more independently addressable subchannels. The transaction assembler combines the shared and independent address components in a reorder table element and issue a single memory transaction.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括分配逻辑，重排序表和事务汇编器。 分配逻辑接收访问存储器通道的请求，并分配请求以访问通道内的两个或更多个可独立寻址的子信道中的一个。 重排序表包括两个或多个表元素。 每个表格元素包括共享地址组件和对应于两个或更多个可独立寻址的子信道中的每一个的独立地址组件。 事务汇编器将重新排序表元素中的共享和独立地址组件合并并发出单个内存事务。
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公开(公告)号：US07382373B2
公开(公告)日：2008-06-03
申请号：US10741808
申请日：2003-12-19
IPC分类号： G06T13/00
摘要： In some embodiments, a method includes generating blurred copies of an object by applying multi-texturing to the object during one pass through a graphics processing pipeline. In some embodiments, a graphics pipeline includes a texture memory and a graphics processor coupled to the texture memory. The texture memory provides a location to store texture information. The graphics processor provides processor to process the texture information by shifting and blending the texture information in one pass through the graphics processor to obtain shifted and blended texture information.
摘要翻译： 在一些实施例中，一种方法包括通过在通过图形处理管线的一次通过期间对对象应用多纹理来生成对象的模糊副本。 在一些实施例中，图形管线包括纹理存储器和耦合到纹理存储器的图形处理器。 纹理记忆库提供了存储纹理信息的位置。 图形处理器通过在一次通过图形处理器中移动和混合纹理信息来提供处理器来处理纹理信息，以获得移位和混合纹理信息。
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公开(公告)号：US20080162802A1
公开(公告)日：2008-07-03
申请号：US11648469
申请日：2006-12-28
申请人： James Akiyama , William H. Clifford
发明人： James Akiyama , William H. Clifford
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0207 , G06F12/0646 , G09G5/395 , G09G2360/122 , G09G2360/123 , G11C8/12 , G11C11/4082
摘要： An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.
摘要翻译： 本发明的一个实施例是一种控制存储器访问的技术。 地址预先转换电路根据访问控制信号条件来处理由处理器提供的地址位。 数据转向电路连接到存储器的N个子通道，以根据与N个子通道相关联的访问控制信号，经调节的地址位和子信道标识符动态地引导包括平铺和直到的存储器访问的存储器访问类型的数据， 频道 平铺内存访问包括水平和垂直平铺的内存访问。 地址后转换电路使用经调节的地址位并根据访问控制信号和子信道标识符向N个子信道生成子信道地址位。
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公开(公告)号：US08878860B2
公开(公告)日：2014-11-04
申请号：US11648469
申请日：2006-12-28
申请人： James Akiyama , William H. Clifford
发明人： James Akiyama , William H. Clifford
CPC分类号： G06F13/1684 , G06F12/0207 , G06F12/0646 , G09G5/395 , G09G2360/122 , G09G2360/123 , G11C8/12 , G11C11/4082
摘要： An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.
摘要翻译： 本发明的一个实施例是一种控制存储器访问的技术。 地址预先转换电路根据访问控制信号条件来处理由处理器提供的地址位。 数据转向电路连接到存储器的N个子通道，以根据与N个子通道相关联的访问控制信号，经调节的地址位和子信道标识符动态地引导包括平铺和直到的存储器访问的存储器访问类型的数据， 频道 平铺内存访问包括水平和垂直平铺的内存访问。 地址后转换电路使用经调节的地址位并根据访问控制信号和子信道标识符向N个子信道生成子信道地址位。
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公开(公告)号：US20100122046A1
公开(公告)日：2010-05-13
申请号：US12690551
申请日：2010-01-20
IPC分类号： G06F12/02
CPC分类号： G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括分配逻辑和事务汇编器。 分配逻辑接收访问存储器通道的请求。 交易汇编器将该请求组合成一个或多个附加请求以访问频道内的两个或更多个可独立寻址的子信道。
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公开(公告)号：US08010754B2
公开(公告)日：2011-08-30
申请号：US12690551
申请日：2010-01-20
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括分配逻辑和事务汇编器。 分配逻辑接收访问存储器通道的请求。 交易汇编器将该请求组合成一个或多个附加请求以访问频道内的两个或更多个可独立寻址的子信道。
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公开(公告)号：US07765366B2
公开(公告)日：2010-07-27
申请号：US11159745
申请日：2005-06-23
CPC分类号： G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括分配逻辑和事务汇编器。 分配逻辑接收访问存储器通道的请求。 交易汇编器将该请求组合成一个或多个附加请求以访问频道内的两个或更多个可独立寻址的子信道。
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8.发明授权Mechanism for assembling memory access requests while speculatively returning data 失效在推测返回数据时组装内存访问请求的机制公开(公告)号：US07587521B2
公开(公告)日：2009-09-08
申请号：US11165390
申请日：2005-06-23
申请人： James Akiyama , William H. Clifford
发明人： James Akiyama , William H. Clifford
CPC分类号： G06F13/1684 , G06F13/1626
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The transaction assembler combines the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and facilitates a speculative return of data from a subchannel for which a subchannel request is not available.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括分配逻辑和事务汇编器。 分配逻辑接收访问存储器通道的请求，并分配请求以访问通道内的两个或更多个可独立寻址的子信道中的一个。 事务汇编器将请求与一个或多个附加请求组合以访问信道内的两个或更多个可独立寻址的子信道，并且促进从子信道请求不可用的子信道的数据的推测返回。
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公开(公告)号：US4227165A
公开(公告)日：1980-10-07
申请号：US5116
申请日：1979-01-22
摘要： A member of a linear position measuring transducer is provided with a hole running parallel to its windings. In one embodiment, elements are inserted into the hole to expand or shorten the length of the transducer. In another embodiment, cutout slots are made between quadrature sections of windings and the elements are introduced into the hole to alter the relative spacing between these quadrature winding sections.
摘要翻译： 线性位置测量传感器的一个构件具有平行于其绕组的孔。 在一个实施例中，将元件插入孔中以扩展或缩短换能器的长度。 在另一个实施例中，在绕组的正交部分之间形成切口槽，并将元件引入孔中以改变这些正交绕组部分之间的相对间隔。
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10.发明授权Media memory system and method for providing concurrent memory access to a plurality of processors through separate translation table information 有权用于通过单独的转换表信息提供对多个处理器的并发存储器访问的媒体存储器系统和方法公开(公告)号：US07490215B2
公开(公告)日：2009-02-10
申请号：US11022503
申请日：2004-12-22
IPC分类号： G06F12/00
CPC分类号： G06F12/1072
摘要： A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
摘要翻译： 一种用于将母处理器地址转换与媒体处理器的地址转换相匹配并通过单独的转换表信息提供对多个媒体处理器的并发存储器访问的方法和装置。 特别地，当媒体应用程序分配要由父处理器和媒体处理器上运行的媒体应用程序共享的内存时，给定媒体应用程序的页面目录将被复制到媒体处理器的页面目录。
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