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    Intelligent network topology and configuration verification using a method of loop detection
    3.
    发明授权
    Intelligent network topology and configuration verification using a method of loop detection 有权
    智能网络拓扑和使用循环检测方法进行配置验证

    公开(公告)号：US06857027B1

    公开(公告)日：2005-02-15

    申请号：US09712610

    申请日：2000-11-14

    申请人： Carl John Lindeborg ,  Mark David Moreau ,  Keith Louis Petry ,  John Ernest Ziegler

    发明人： Carl John Lindeborg ,  Mark David Moreau ,  Keith Louis Petry ,  John Ernest Ziegler

    IPC分类号： G06F15/16 ,  G06F15/173 ,  H04L12/46

    CPC分类号： H04L12/46

    摘要： A system and method are disclosed for detecting and preventing bridge loops in a relatively low cost bridge module designed for installation in a network hub. The bridge operates to monitor an intra-hub communication path of the network hub to detect bridge protocol data units transmitted by a switching fabric within the network hub. The bridge module stores a MAC source address of a bridge protocol data unit detected on the intra-hub communications path, and forwards the bridge protocol data unit through its external communication ports to respective network segments. The bridge module monitors its external communication ports for any data unit having a destination address matching a bridge multicast address. When a data unit having a destination address matching the bridge multicast address is detected, the bridge module compares the MAC source address of that data unit to the previously stored MAC source address from the bridge protocol data unit detected on the intra-hub communication path. In the event that the MAC source address of the data unit detected on the external communication port matches the previously stored MAC source address, the bridge module disables operation of the respective one of its external communication ports at which the data unit was received. In one embodiment of the disclosed system, the bridge module further monitors its external communications ports for routing protocol messages. In the event that a routing protocol message is detected on one of those external communications ports, the bridge module disables that port.

    摘要翻译： 公开了一种系统和方法，用于检测和防止设计用于安装在网络集线器中的相对低成本的桥接模块中的桥接环路。 桥接器用于监视网络集线器的集线器内通信路径以检测由网络集线器内的交换结构发送的桥协议数据单元。 桥模块存储在集线器内通信路径上检测到的桥协议数据单元的MAC源地址，并通过其外部通信端口将桥协议数据单元转发到各网段。 桥模块监视其外部通信端口，用于具有匹配桥多播地址的目的地地址的任何数据单元。 当检测到具有匹配桥接组播地址的目的地地址的数据单元时，桥模块从在集线器内通信路径上检测到的桥协议数据单元将该数据单元的MAC源地址与先前存储的MAC源地址进行比较。 在外部通信端口检测到的数据单元的MAC源地址匹配先前存储的MAC源地址的情况下，桥接模块禁止其接收到数据单元的相应一个外部通信端口的操作。 在所公开的系统的一个实施例中，网桥模块还监视其外部通信端口以路由协议消息。 在这些外部通信端口之一上检测到路由协议消息的情况下，桥接器模块将禁用该端口。

    Transmit queue caching
    4.
    发明授权
    Transmit queue caching 失效
    传输队列缓存

    公开(公告)号：US06735210B1

    公开(公告)日：2004-05-11

    申请号：US09507256

    申请日：2000-02-18

    申请人： Carl John Lindeborg ,  James Scott Hiscock ,  David James Mannion

    发明人： Carl John Lindeborg ,  James Scott Hiscock ,  David James Mannion

    IPC分类号： H04L1256

    CPC分类号： H04L49/3027 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/503

    摘要： A computer network switch includes a receiving module for receiving packets, a packet memory with a plurality of buffer cells with each of the buffer cells having a buffer descriptor. A descriptor free pool lists available buffer descriptors that can be used for new incoming packets. A plurality of transmit queues hold the buffer descriptors. Each of the transmit queues include an input queue, an expansion queue and an output queue. The switch also includes control logic for directing the removing of one of the available buffer descriptors from the free pool and directing one of the packets from the receiving module into one of the buff cells corresponding to the one available buffer descriptor. The control logic places the one buffer descriptor in the input queue of one of the transmit queues. The control logic also monitors a load status of the input and output queues.

    摘要翻译： 计算机网络交换机包括用于接收分组的接收模块，具有多个缓冲器单元的分组存储器，每个缓冲器单元具有缓冲器描述符。 描述符空闲池列出了可用于新的传入数据包的可用缓冲区描述符。 多个发送队列保存缓冲器描述符。 每个发送队列包括输入队列，扩展队列和输出队列。 该交换机还包括控制逻辑，用于引导从空闲池中移除可用的缓冲器描述符中的一个，并将来自接收模块的一个分组引导到与一个可用缓冲区描述符对应的一个buff单元中。 控制逻辑将一个缓冲区描述符放置在发送队列之一的输入队列中。 控制逻辑还监视输入和输出队列的负载状态。

    Method and apparatus to detect lost buffers with a descriptor based queue
    5.
    发明授权
    Method and apparatus to detect lost buffers with a descriptor based queue 失效
    用基于描述符的队列检测丢失缓冲区的方法和装置

    公开(公告)号：US06532503B1

    公开(公告)日：2003-03-11

    申请号：US09507358

    申请日：2000-02-18

    申请人： Carl John Lindeborg ,  James Scott Hiscock ,  Normand Louis Magnan ,  John Ernest Ziegler

    发明人： Carl John Lindeborg ,  James Scott Hiscock ,  Normand Louis Magnan ,  John Ernest Ziegler

    IPC分类号： G06F1300

    CPC分类号： H04L49/90

    摘要： A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

    摘要翻译： 主数据存储器被提供在网络设备中并且包括用于存储数据分组的多个缓冲器。 多个描述符或指针指向各个缓冲器。 描述符的状态存储在描述符引用存储器中。 状态信息包括描述符是处于活动状态还是空闲状态，以及发送队列中描述符的副本的指示。 描述符空闲池包括在空闲状态下的描述符列表。

    Method and apparatus for detecting duplicate buffers in a descriptor based multi-port queue
    6.
    发明授权
    Method and apparatus for detecting duplicate buffers in a descriptor based multi-port queue 失效
    用于检测基于描述符的多端口队列中的重复缓冲器的方法和装置

    公开(公告)号：US06556579B1

    公开(公告)日：2003-04-29

    申请号：US09400330

    申请日：1999-09-21

    申请人： Carl John Lindeborg ,  James Scott Hiscock ,  Normand Louis Magnan ,  John Ernest Ziegler

    发明人： Carl John Lindeborg ,  James Scott Hiscock ,  Normand Louis Magnan ,  John Ernest Ziegler

    IPC分类号： H04L1228

    CPC分类号： H04L49/90

    摘要： A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

    摘要翻译： 主数据存储器被提供在网络设备中并且包括用于存储数据分组的多个缓冲器。 多个描述符或指针指向各个缓冲器。 描述符的状态存储在描述符引用存储器中。 状态信息包括描述符是处于活动状态还是空闲状态，以及发送队列中描述符的副本的指示。 描述符空闲池包括在空闲状态下的描述符列表。

    LAN to ATM backbone switch module
    7.
    发明授权
    LAN to ATM backbone switch module 失效
    LAN到ATM主干交换机模块

    公开(公告)号：US6052383A

    公开(公告)日：2000-04-18

    申请号：US865242

    申请日：1997-05-29

    申请人： David Stoner ,  Carl John Lindeborg ,  Norm Magnan

    发明人： David Stoner ,  Carl John Lindeborg ,  Norm Magnan

    IPC分类号： H04L12/46 ,  H04L12/56 ,  H04Q11/04 ,  H04T3/16 ,  H04L12/28

    CPC分类号： H04L49/309 ,  H04L12/4608 ,  H04Q11/0478 ,  H04L2012/5618 ,  H04L2012/5665

    摘要： A LAN to ATM switch module includes a memory with an ATM port, a LAN port and a processor port. Each of port separately reading and writing information to/from the memory. An ATM interface is included for reading information from the ATM port and converting the information into an ATM format. The ATM interface also converts ATM format information to be delivered to the ATM port and written to the memory. A LAN interface reads information from the LAN port and converts the information into LAN format. The LAN interface also converts LAN information from a LAN packet channel bus to the LAN port, to be written to the memory. The switch module also includes a processor for reading information in the memory through the processor port. The processor determines the processing need for the information, the processor modifies the information in the memory according to the processing needed by writing to the memory through the processor port and controlling the ATM and LAN interfaces according to the processing needed.

    摘要翻译： LAN到ATM交换机模块包括具有ATM端口，LAN端口和处理器端口的存储器。 每个端口分别读取和写入信息到内存。 ATM接口包括用于从ATM端口读取信息并将信息转换成ATM格式。 ATM接口还将要传送到ATM端口的ATM格式信息转换并写入存储器。 LAN接口从LAN端口读取信息，并将信息转换为LAN格式。 LAN接口还将LAN信息从LAN分组信道总线转换为LAN端口，以将其写入存储器。 交换模块还包括一个处理器，用于通过处理器端口读取存储器中的信息。 处理器确定对信息的处理需求，处理器根据通过处理器端口写入存储器所需的处理来修改存储器中的信息，并根据所需的处理来控制ATM和LAN接口。

    Multiported memory access system with arbitration and a source burst limiter for blocking a memory access request
    8.
    发明授权
    Multiported memory access system with arbitration and a source burst limiter for blocking a memory access request 失效
    具有仲裁的多端口存储器访问系统和用于阻塞存储器访问请求的源突发限制器

    公开(公告)号：US6032232A

    公开(公告)日：2000-02-29

    申请号：US865243

    申请日：1997-05-29

    申请人： Carl John Lindeborg ,  David Stoner

    发明人： Carl John Lindeborg ,  David Stoner

    IPC分类号： G06F13/18 ,  G06F12/00 ,  G06F13/28

    CPC分类号： G06F13/18

    摘要： A multiport or multiported memory device is provided. A first user and at least a second user are provided. A multilevel memory arbitration system is implemented which establishes arbitration cycles wherein the high priority user is granted priority as to access either during each arbitration cycle or during a greater number of arbitration cycles. A source burst limiter is provided associated with the high priority user. The source burst limiter monitors access of the high priority user to the multiport memory and limits such access based on a comparison of access attributes to some access attribute threshold.

    摘要翻译： 提供多端口或多端口存储器件。 提供第一用户和至少第二用户。 实施多级存储器仲裁系统，其建立仲裁周期，其中高优先级用户被授予在每个仲裁周期期间或在更大数量的仲裁周期期间访问的优先级。 提供与高优先级用户相关联的源突发限制器。 源突发限制器监视高优先级用户对多端口存储器的访问，并且基于访问属性与某些访问属性阈值的比较来限制这种访问。