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1.发明授权Apparatus and method for operating chips synchronously at speeds exceeding the bus speed 失效以超过总线速度的速度同步运行芯片的装置和方法
公开(公告)号：US5708801A
公开(公告)日：1998-01-13
申请号：US744387
申请日：1996-11-07
CPC分类号： G06F1/06 , G06F13/4217
摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.
摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N是 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。
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2.发明授权Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer 失效时钟产生装置，用于产生响应于同步信号的N-1 / N频率同步的总线时钟和芯片时钟，用于禁止数据传送
公开(公告)号：US5600824A
公开(公告)日：1997-02-04
申请号：US191865
申请日：1994-02-04
CPC分类号： G06F1/06 , G06F13/4217
摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.
摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N为 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。
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