公开(公告)号：US5600824A

公开(公告)日：1997-02-04

申请号：US191865

申请日：1994-02-04

申请人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

发明人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

IPC分类号： G06F1/06 ,  G06F13/42 ,  G06F1/04

CPC分类号： G06F1/06 ,  G06F13/4217

摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N为 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。

公开(公告)号：US5708801A

公开(公告)日：1998-01-13

申请号：US744387

申请日：1996-11-07

申请人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

发明人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

IPC分类号： G06F1/06 ,  G06F13/42 ,  G06F1/12

CPC分类号： G06F1/06 ,  G06F13/4217

摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N是 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。

公开(公告)号：US06049851A

公开(公告)日：2000-04-11

申请号：US196618

申请日：1994-02-14

申请人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

发明人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

IPC分类号： G06F12/08 ,  G06F9/34

CPC分类号： G06F12/0831

摘要： A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

摘要翻译： 具有高速缓存和相干I / O和多处理器计算机系统的单处理器计算机系统中的双缓存窥探机制减少了在一致性检查期间处理器停顿的周期数。 侦听机制分割每个相关性检查，以便首先将只读检查发送到高速缓存子系统，然后只有在只读检查期间存在高速缓存命中时才会发送读写检查，并且存在 需要修改缓存。 即使缓存命中导致额外的一致性检查，平均处理器流水线停止时间也减少，因为大多数一致性检查不会导致缓存命中。

公开(公告)号：US5519838A

公开(公告)日：1996-05-21

申请号：US201186

申请日：1994-02-24

申请人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert E. Naas ,  Robert D. Odineal ,  Brendan A. Voge ,  James B. Williams ,  John L. Wood

发明人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert E. Naas ,  Robert D. Odineal ,  Brendan A. Voge ,  James B. Williams ,  John L. Wood

IPC分类号： G06F13/368 ,  G06F13/00

CPC分类号： G06F13/368

摘要： A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle. Each arbitration signal processor preferably is also responsive to the client option signals sent by the host module during an earlier cycle.

摘要翻译： 具有总线仲裁方案的总线系统。 总线系统包括总线和耦合到总线的多个客户端模块。 每个客户端模块能够将总线上的信息发送到客户端模块的另一个，只有一个客户端模块有权在任何时候在总线上传输信息。 有权在总线上传输信息的模块可以控制总线最短时间来定义一个周期。 为了确定哪个模块有权使用总线，当客户端模块试图在总线上传输信息时，每个客户端模块都会产生仲裁信号。 每个客户端模块具有响应于仲裁信号的仲裁信号处理器，用于确定模块是否有权在所述总线上发送信息。 系统还优选地还包括主机模块，其向客户端模块通知在给定周期中在总线上允许的交易类型。 每个仲裁信号处理器优选地还响应于在较早的周期期间由主机模块发送的客户端选项信号。

公开(公告)号：US5530933A

公开(公告)日：1996-06-25

申请号：US201463

申请日：1994-02-24

申请人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

发明人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0831

摘要： A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

摘要翻译： 与具有总线的系统一起使用的一致性方案，主存储器，用于响应于在总线上接收到的事务来访问主存储器的主存储器控制器，以及耦合到总线的一组处理器模块。 每个处理器模块具有高速缓冲存储器，并且能够将总线上的相干事务发送到其他处理器模块和主存储器控制器。 每个处理器模块检测总线上发出的相干事务，并执行每个相干事务的高速缓存一致性检查。 每个处理器模块具有用于存储在总线上发布的所有事务的一致性队列，并且用于以先入先出顺序执行事务的一致性检查。 当模块在总线上传输一致的事务时，它将自己的事务置于自己的一致性队列中。

公开(公告)号：US20090221473A1

公开(公告)日：2009-09-03

申请号：US12088846

申请日：2005-09-30

申请人： Kenneth K. Chan ,  Jin Xiao

发明人： Kenneth K. Chan ,  Jin Xiao

IPC分类号： A61K38/12 ,  C12N5/06 ,  A61P35/02

CPC分类号： A61K38/15 ,  A61K38/12

摘要： Compounds and methods useful for the treatment of cancer in subjects in need of such treatment. The compounds are metabolites of the compound FK228 which have been identified as possessing HDAC inhibitory activity and anticancer properties. Further provided are compounds and methods for inducing apoptosis in cancer cells. Further provided are compounds and methods for inhibiting HDAC in cancer cells.

摘要翻译： 可用于治疗需要这种治疗的受试者中的癌症的化合物和方法。 这些化合物是化合物FK228的代谢物，其被鉴定为具有HDAC抑制活性和抗癌特性。 还提供了诱导癌细胞凋亡的化合物和方法。 还提供了用于抑制癌细胞中HDAC的化合物和方法。

公开(公告)号：US20110027798A1

公开(公告)日：2011-02-03

申请号：US12935775

申请日：2009-03-31

申请人： Kenneth K. Chan ,  Zhongfa Liu ,  Zhiliang Xie ,  Guido Marcucci ,  John C. Byrd ,  Natarajan Muthusamy ,  Ramiro Garzon ,  Shujun Lui

发明人： Kenneth K. Chan ,  Zhongfa Liu ,  Zhiliang Xie ,  Guido Marcucci ,  John C. Byrd ,  Natarajan Muthusamy ,  Ramiro Garzon ,  Shujun Lui

IPC分类号： C12Q1/68 ,  C07H21/04

CPC分类号： C12Q1/6816 ,  C12Q1/6834 ,  C12Q2561/125 ,  C12Q2525/207 ,  C12Q2521/307 ,  C12Q2563/131

摘要： Described herein is a method for the qualitative and/or quantitative determination of an analyte in a test sample which includes base pairing at least one oligonucleotide to a capture template having an overhang; and, hybridizing with a detection probe.

摘要翻译： 本文描述了用于定性和/或定量测定测试样品中分析物的方法，该方法包括将至少一种寡核苷酸与具有突出端的捕获模板碱基配对; 并与检测探针杂交。

公开(公告)号：US5559877A

公开(公告)日：1996-09-24

申请号：US407171

申请日：1995-03-21

申请人： Gerald R. Ash ,  Kenneth K. Chan ,  Jiayu Chen ,  Alan E. Frey ,  James J. Gallagher ,  Andrew W. Peck

发明人： Gerald R. Ash ,  Kenneth K. Chan ,  Jiayu Chen ,  Alan E. Frey ,  James J. Gallagher ,  Andrew W. Peck

IPC分类号： H04Q3/545 ,  H04M3/00 ,  H04M3/64 ,  H04M7/00 ,  H04Q3/66

CPC分类号： H04Q3/66 ,  H04Q2213/13144 ,  H04Q2213/13176 ,  H04Q2213/13251 ,  H04Q2213/13353

摘要： A telecommunication network may be arranged in accord with the invention so that a change in provisioning data occurring at one element of the network is automatically supplied to the other elements of the network, thereby eliminating the need of having a network administration facility to communicate manually the change to the other network elements. For example, if a local central office switch is rehomed from a first toll switch to a second toll switch, then the first and second toll switches form messages respectively characterizing the rehome and then send the messages to each of the other network toll switches so that the other toll switches may update their respective routing and trunking data relating to the rehomed switch. The network is also arranged to implement a rule-based, end-to-end routing scheme which automatically selects a routing path from multiple candidates based on (a) class-of-service parameters and (b) availability of network capacity. The automatic selection of a routing path thus replaces the provisioning of routing data in the toll switches, which data was priorly needed to select the appropriate routing path.

摘要翻译： 可以根据本发明布置电信网络，使得在网络的一个元件处发生的供应数据的变化被自动地提供给网络的其他元件，从而不需要使网络管理设备手动地通信 改为其他网元。 例如，如果本地中心局交换机从第一个长途交换机重新连接到第二个长途交换机，则第一和第二个长途交换机形成分别表征该路由的消息，然后将消息发送到每个其他网络长途交换机，使得 其他长途交换机可以更新其与被重新连接的交换机有关的各自的路由和中继数据。 该网络还被设置为实现基于规则的端到端路由方案，其基于（a）服务等级参数和（b）网络容量的可用性自动从多个候选者中选择路由路径。 因此，路由路径的自动选择因此取代了长途交换机中路由数据的供应，先前需要哪些数据来选择适当的路由路径。

公开(公告)号：US5464496A

公开(公告)日：1995-11-07

申请号：US250643

申请日：1994-05-27

申请人： Michael L. Wilson ,  Kenneth K. Chan

发明人： Michael L. Wilson ,  Kenneth K. Chan

IPC分类号： B29C65/20 ,  B32B35/00

CPC分类号： B29C66/5221 ,  B29C65/2092 ,  B29C66/1142 ,  B29L2023/22 ,  Y10T74/18808 ,  Y10T74/1967

摘要： A plastic pipe butt fusion machine has a base, a clamp on the base for securing a first length of plastic pipe, a second clamp mounted on the base for securing a second length of plastic pipe to be fusion welded to the first in axial end-to-end alignment, the second clamp being moveable relative to the base, a spring positioned between the second clamp and the base so that when the spring is tension loaded the second clamp is urged in the direction toward the first clamp to thereby resiliently urge the plastic pipes held by the first and second clamps into axial abutted relationship during fusion.

摘要翻译： 塑料管对接融合机具有基座，基座上的夹具，用于固定第一长度的塑料管，第二夹具安装在基座上，用于固定第二长度的塑料管，以熔化焊接到第一轴向端部， 端部对准，第二夹具相对于基座可移动，弹簧定位在第二夹具和基座之间，使得当弹簧被拉紧时，第二夹具沿着朝向第一夹具的方向被推动，从而弹性地推动 在第一和第二夹具处固定的塑料管道在融合期间成轴向抵接关系。

公开(公告)号：US08046639B1

公开(公告)日：2011-10-25

申请号：US12846653

申请日：2010-07-29

申请人： Grace Y. Nordin ,  Rakesh Mehta ,  Kenneth K. Chan

发明人： Grace Y. Nordin ,  Rakesh Mehta ,  Kenneth K. Chan

IPC分类号： G06F11/00

CPC分类号： G06F11/2268

摘要： A system and method for accurately modeling a fault log is provided for validating one or more elements of fault detection and logging logic for a real-time fault log of a digital system such as, for instance, a computer processor. The method includes injecting one or more known faults into a data path and/or a control path of the computer processor and spawning an individual tracking thread for each of the injected faults. The tracking threads may be synchronized at a predefined synchronization point that is selected as a function of a collective logging delay representing the time required for each of the injected faults to reach a real-time logging point within the computer processor. Once synchronized, the tracking threads may be input into a fault logging specification for fault behavior and/or system impact modeling and fault prioritization for use in generating a fault log model for comparison to the real-time fault log maintained within the computer processor.

摘要翻译： 提供了一种用于对故障日志进行精确建模的系统和方法，用于验证数字系统（例如计算机处理器）的实时故障日志的故障检测和记录逻辑的一个或多个元件。 该方法包括将一个或多个已知故障注入到计算机处理器的数据路径和/或控制路径中，并为每个注入的故障产生单独的跟踪线程。 跟踪线程可以在预定义的同步点同步，该预定义同步点被选择为集体记录延迟的函数，其表示每个注入的故障到达计算机处理器内的实时记录点所需的时间。 一旦同步，跟踪线程可以被输入到用于故障行为和/或系统影响建模和故障优先级的故障记录规范中，以用于生成故障日志模型以与计算机处理器内维护的实时故障日志进行比较。