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    Memory controller configurable to allow bandwidth/latency tradeoff
    1.
    发明授权
    Memory controller configurable to allow bandwidth/latency tradeoff 有权
    内存控制器可配置为允许带宽/延迟权衡

    公开(公告)号：US07526626B2

    公开(公告)日：2009-04-28

    申请号：US11891955

    申请日：2007-08-14

    申请人： James Daniel Kelly

    发明人： James Daniel Kelly

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1684

    摘要： A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.

    摘要翻译： 存储器控制器包括多个通道控制电路。 多个信道控制电路中的每一个耦合到耦合到存储器系统的多个信道中的相应一个信道。 多个信道控制电路被耦合以接收多个信道是否组合的指示。 响应于指示多个通道被组合的指示，数据被传送给多个通道中的每一个上的第一命令。 响应于指示多个信道不联动的指示，在多个信道的选定信道上传送用于第一命令的数据。 在一些实施例中，存储器控制器可以与一个或多个处理器集成。

    Distributing primitives to multiple rasterizers
    3.
    发明授权
    Distributing primitives to multiple rasterizers 有权
    将原语分发到多个光栅化器

    公开(公告)号：US09536341B1

    公开(公告)日：2017-01-03

    申请号：US12581746

    申请日：2009-10-19

    申请人： Johnny S. Rhoades ,  Emmett M. Kilgariff ,  Michael C. Shebanow ,  Ziyad S. Hakura ,  Dale L. Kirkland ,  James Daniel Kelly

    发明人： Johnny S. Rhoades ,  Emmett M. Kilgariff ,  Michael C. Shebanow ,  Ziyad S. Hakura ,  Dale L. Kirkland ,  James Daniel Kelly

    IPC分类号： G06F15/80 ,  G06T15/00

    CPC分类号： G06T15/005 ,  G06T2210/52

    摘要： One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

    摘要翻译： 本发明的一个实施例提出了一种用于将原语并行分配到多个光栅化器的技术。 多个独立的几何单元在不同的图形基元上同时执行几何处理。 原始分配方案以每个时钟的多个基元的速率将原始图元从多个几何单元同时传送到多个光栅化器。 多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

    Memory controller configurable to allow bandwidth/latency tradeoff
    4.
    发明授权
    Memory controller configurable to allow bandwidth/latency tradeoff 有权
    内存控制器可配置为允许带宽/延迟权衡

    公开(公告)号：US07269709B2

    公开(公告)日：2007-09-11

    申请号：US10269913

    申请日：2002-10-11

    申请人： James Daniel Kelly

    发明人： James Daniel Kelly

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1684

    摘要： A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.

    摘要翻译： 存储器控制器包括多个通道控制电路。 多个信道控制电路中的每一个耦合到耦合到存储器系统的多个信道中的相应一个信道。 多个信道控制电路被耦合以接收多个信道是否组合的指示。 响应于指示多个通道被组合的指示，数据被传送给多个通道中的每一个上的第一命令。 响应于指示多个信道不联动的指示，在多个信道的选定信道上为第一命令传送数据。 在一些实施例中，存储器控制器可以与一个或多个处理器集成。