公开(公告)号：US08665009B2

公开(公告)日：2014-03-04

申请号：US13562516

申请日：2012-07-31

申请人： James Edward Myers ,  Parameshwarappa Anand Kumar Savanth ,  David Walter Flynn ,  David William Howard ,  Bal S Sandhu

发明人： James Edward Myers ,  Parameshwarappa Anand Kumar Savanth ,  David Walter Flynn ,  David William Howard ,  Bal S Sandhu

IPC分类号： H01J19/82 ,  G11C5/14

CPC分类号： H02M3/07

摘要： An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry. This provides a particularly simple and effective mechanism for providing an additional load on the output node which can be altered with the aim of offsetting variation in the load on the output node presented by the circuit block, thus allowing the variation in the voltage output from the on-chip voltage generation circuitry to be controlled.

摘要翻译： 提供一种用于控制片上电压产生电路的电压输出变化的集成电路和方法。 集成电路包括电压产生电路，其被配置为从提供的输入电压进行操作，并且在输出节点处产生不同于所提供的输入电压的片上电压。 然后，电路块被布置成在电路块的操作期间接收由电压产生电路产生的片上电压源，该电路块在输出节点上呈现变化的负载。 振荡电路还耦合到输出节点以在输出节点上提供额外的负载，并且被配置为产生其频率随着片上电压供应的值变化而变化的振荡信号。 控制电路被配置为响应于触发条件来调节由振荡电路在输出节点上提供的附加负载。 这提供了一种特别简单和有效的机制，用于在输出节点上提供额外的负载，其可以被改变，目的是抵消由电路块呈现的输出节点上的负载的变化，从而允许来自 片上电压产生电路要被控制。

公开(公告)号：US08868962B2

公开(公告)日：2014-10-21

申请号：US13368383

申请日：2012-02-08

申请人： James Edward Myers ,  David Walter Flynn ,  Bal S Sandhu

发明人： James Edward Myers ,  David Walter Flynn ,  Bal S Sandhu

IPC分类号： G06F1/04 ,  G01K7/00

CPC分类号： G01K7/346

摘要： A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature.

摘要翻译： 集成电路的监视电路包括非温度反相电路和温度反相电路。 测量两个电路的工作参数，表示各个电路中信号的传播速度。 响应于温度变化，非温度反相电路减慢，温度反转电路加速。 相比之下，响应于工作电压的变化，两个电路都加速或减慢。 响应于温度的这种分歧和对电压的类似响应使得监测电路能够区分工作电压的变化和工作温度的变化。

公开(公告)号：US08451026B2

公开(公告)日：2013-05-28

申请号：US13067182

申请日：2011-05-13

申请人： John Philip Biggs ,  James Edward Myers ,  David William Howard ,  David Walter Flynn ,  Carsten Tradowsky

发明人： John Philip Biggs ,  James Edward Myers ,  David William Howard ,  David Walter Flynn ,  Carsten Tradowsky

IPC分类号： H01L25/00 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/78 ,  H01L27/11807 ,  H01L2027/11881

摘要： An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.

摘要翻译： 公开了集成电路，使用标准单元生成这种集成电路的布局的方法以及提供这种标准单元的标准单元库。 生成布局的方法包括形成多个行，并且根据集成电路所需的功能部件选择多个标准单元填充每行，每个标准单元具有邻接至少的邻接区域的邻接区域 行中一个相邻的标准单元格。 在每排中，该行中的每个标准单元被布置成具有与公共路线轨迹对准的电压连接区域，但是每个标准单元具有其电压连接区域被配置为不在标准的整个宽度上延伸 细胞。 在每排中，对于行中的每个标准单元，该标准单元的电压连接区域然后连接到关于由标准单元定义的相应功能组件的电压要求的多个电压源中的一个，并且独立 的每个相邻单元连接到的电压源。 这为布局操作期间放置标准单元提供了一种特别灵活的机制，因为运行相同电压源所需的标准单元不再需要放在一起。

公开(公告)号：US20120286858A1

公开(公告)日：2012-11-15

申请号：US13067182

申请日：2011-05-13

申请人： John Philip Biggs ,  James Edward Myers ,  David William Howard ,  David Walter Flynn ,  Carsten Tradowsky

发明人： John Philip Biggs ,  James Edward Myers ,  David William Howard ,  David Walter Flynn ,  Carsten Tradowsky

IPC分类号： H01L25/00 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/78 ,  H01L27/11807 ,  H01L2027/11881

摘要： An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.

摘要翻译： 公开了集成电路，使用标准单元生成这种集成电路的布局的方法以及提供这种标准单元的标准单元库。 生成布局的方法包括形成多个行，并且根据集成电路所需的功能部件选择多个标准单元填充每行，每个标准单元具有邻接至少的邻接区域的邻接区域 行中一个相邻的标准单元格。 在每排中，该行中的每个标准单元被布置成具有与公共路线轨迹对准的电压连接区域，但是每个标准单元具有其电压连接区域被配置为不在标准的整个宽度上延伸 细胞。 在每排中，对于行中的每个标准单元，该标准单元的电压连接区域然后连接到关于由标准单元定义的相应功能组件的电压要求的多个电压源中的一个，并且独立 的每个相邻单元连接到的电压源。 这为布局操作期间放置标准单元提供了一种特别灵活的机制，因为运行相同电压源所需的标准单元不再需要放在一起。

公开(公告)号：US20120286824A1

公开(公告)日：2012-11-15

申请号：US13067184

申请日：2011-05-13

申请人： James Edward Myers ,  David Walter Flynn ,  Robert Campbell Aitken ,  Marlin Wayne Frederick, JR.

发明人： James Edward Myers ,  David Walter Flynn ,  Robert Campbell Aitken ,  Marlin Wayne Frederick, JR.

IPC分类号： H03K19/096 ,  G06F17/50

CPC分类号： H03K19/0013 ,  G06F17/5059 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84 ,  H03K19/0016

摘要： A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The clock gating circuitry unit receives a clock signal, a clock enable signal having either an enable value indicating the plurality of synchronous elements to are currently functional and are to be clocked, or a disable value indicating the plurality of synchronous elements are currently not required and are not to be clocked, and a power mode signal having either a low power value indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down, or a functional mode value indicating the plurality of synchronous elements are to be powered. The clock gating unit has logic circuitry that is configured in response to the clock enable signal having the enable value and to the low power mode signal having the functional mode value to output the clock signal and in response to at least one of the clock enable signal having the disable value and the low power mode signal having the low power value to output the predetermined gated value.

摘要翻译： 公开了一种用于向集成电路内的多个同步元件提供时钟信号或预定门控值的时钟选通电路单元。 时钟选通电路被配置为接收时钟信号并输出​​包括时钟信号或预定门控值的输出信号。 时钟门控电路单元接收时钟信号，时钟使能信号具有指示多个同步元件的使能值当前正在工作并且要被计时，或者当前不需要指示多个同步元件的禁用值， 以及功率模式信号，其具有指示进入低功率模式的低功率值，其中所述多个同步元件的至少一部分被供电以保持数据并且不被计时，并且至少另外 多个同步元件的一部分被断电，或者指示多个同步元件的功能模式值被供电。 时钟门控单元具有逻辑电路，其被配置为响应于具有使能值的时钟使能信号和具有功能模式值的低功率模式信号来输出时钟信号，并且响应于时钟使能信号中的至少一个 具有禁用值和具有低功率值的低功率模式信号以输出预定的门控值。

公开(公告)号：US08922247B2

公开(公告)日：2014-12-30

申请号：US12926498

申请日：2010-11-22

申请人： James Edward Myers ,  David Walter Flynn ,  John Philip Biggs

发明人： James Edward Myers ,  David Walter Flynn ,  John Philip Biggs

IPC分类号： H03K19/094 ,  H03K19/096 ,  H03K3/00 ,  H03B1/00 ,  G06F17/50 ,  H03K19/00

CPC分类号： G06F17/5068 ,  G06F2217/78 ,  H03K19/0016

摘要： A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device. A further data structure corresponding to a standard cell is provided comprising an overdriven retention switching device and a voltage switching device and yet a further standard cell data structure is provided comprising an overdriven voltage switching device.

摘要翻译： 提供了一种功率控制集成电路，其具有电压切换装置和保持开关装置，其具有来自过驱动电压源的输入，使得在保持使能配置中，保持开关装置相对于被耦合到并被驱动 从与电压切换装置相关联的电压输入信号。 提供过载保持开关装置作为与电压开关装置本身的分离实体，并且提供计算机可读存储介质，其存储包括标准单元电路定义的数据结构，用于生成验证集成的电路单元的电路布局 电路。 电路单元包括过驱动保持开关装置。 提供了与标准单元相对应的另外的数据结构，其包括过驱动保持开关装置和电压开关装置，并且还提供了包括过驱动电压开关装置的另外的标准单元数据结构。

公开(公告)号：US20120326772A1

公开(公告)日：2012-12-27

申请号：US13067776

申请日：2011-06-24

申请人： James Edward Myers ,  David Walter Flynn

发明人： James Edward Myers ,  David Walter Flynn

IPC分类号： G05F3/02 ,  G06F17/50

CPC分类号： H03K19/0016

摘要： An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry.

摘要翻译： 集成电路包括主电源轨，接地电源轨以及虚拟主电源轨和虚拟接地电源轨。 组合逻辑电路连接起来，从虚拟主电源轨和虚拟接地电源轨中抽取电力。 信号值存储电路被连接以从主电力轨和地电源轨之一拉动其电力，而另一个电力连接是虚拟轨道。 集成电路具有操作模式，保持模式和关机模式。 在保持模式中，组合逻辑电路之间的电压差是不足以支持数据处理操作的低功率电压差，而信号值存储电路两端的电压差较高，足以支持信号值存储器内的信号值保持 电路。

公开(公告)号：US20120286850A1

公开(公告)日：2012-11-15

申请号：US13067183

申请日：2011-05-13

申请人： James Edward Myers ,  John Philip Biggs ,  David Walter Flynn ,  Carsten Tradowsky

发明人： James Edward Myers ,  John Philip Biggs ,  David Walter Flynn ,  Carsten Tradowsky

IPC分类号： G11C5/14

CPC分类号： G11C14/0054

摘要： Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.

摘要翻译： 描述了以支持Z形电源门控的主从锁存器的形式存储数据值的装置。 在锁存器的输出处的NAND门52在保持模式期间迫使来自锁存器的输出处的预定保持信号值。 在锁存器的输入处的扫描多路复用器42在保持模式期间选择作为来自另一锁存器的预定保持信号的扫描输入。 在闩锁电源选通电路32内，使用虚拟电源轨VDDZ和VSSZ进行Z形电源门控，以减少漏电流。 状态存储电路34永久地连接到电源VDDG，VSSG，使得能够在保持模式期间保持其中存储的任何信号值。

公开(公告)号：US20110181343A1

公开(公告)日：2011-07-28

申请号：US12926498

申请日：2010-11-22

申请人： James Edward Myers ,  David Walter Flynn ,  John Philip Biggs

发明人： James Edward Myers ,  David Walter Flynn ,  John Philip Biggs

IPC分类号： H03K17/687 ,  H03K17/00 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/78 ,  H03K19/0016

摘要： A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device. A further data structure corresponding to a standard cell is provided comprising an overdriven retention switching device and a voltage switching device and yet a further standard cell data structure is provided comprising an overdriven voltage switching device.

摘要翻译： 提供了一种功率控制集成电路，其具有电压切换装置和保持开关装置，其具有来自过驱动电压源的输入，使得在保持使能配置中，保持开关装置相对于被耦合到并被驱动 从与电压切换装置相关联的电压输入信号。 提供过载保持开关装置作为与电压开关装置本身的单独实体，并且提供计算机可读存储介质，其存储包括标准单元电路定义的数据结构，用于生成验证集成的电路单元的电路布局 电路。 电路单元包括过驱动保持开关装置。 提供了与标准单元相对应的另外的数据结构，其包括过驱动保持开关装置和电压开关装置，并且还提供了包括过驱动电压开关装置的另外的标准单元数据结构。

公开(公告)号：US08456223B2

公开(公告)日：2013-06-04

申请号：US13067776

申请日：2011-06-24

申请人： James Edward Myers ,  David Walter Flynn

发明人： James Edward Myers ,  David Walter Flynn

IPC分类号： H03K3/01

CPC分类号： H03K19/0016

摘要： An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry.

摘要翻译： 集成电路包括主电源轨，接地电源轨以及虚拟主电源轨和虚拟接地电源轨。 组合逻辑电路连接起来，从虚拟主电源轨和虚拟接地电源轨中抽取电力。 信号值存储电路被连接以从主电力轨和地电源轨之一拉动其电力，而另一个电力连接是虚拟轨道。 集成电路具有操作模式，保持模式和关机模式。 在保持模式下，组合逻辑电路之间的电压差是不足以支持数据处理操作的低功率电压差，而信号值存储电路两端的电压差较高，足以支持信号值存储器内的信号值保持 电路。