公开(公告)号：US4115852A

公开(公告)日：1978-09-19

申请号：US748179

申请日：1976-12-07

申请人： James O. Rozell

发明人： James O. Rozell

IPC分类号： G06F9/22 ,  G06F13/12 ,  G06F9/16

CPC分类号： G06F9/226 ,  G06F13/124

摘要： A microprogrammed controller for interconnection between a central processor unit and at least one peripheral unit for controlling the transfer of data therebetween in response to instructions from the central processor unit provides for simplified bit manipulation through a feedback circuit which feeds the data to be supplied to the peripheral unit back to the input bus of the controller for further processing. In this way bit manipulation can be accomplished with a single microinstruction to provide for higher speed and efficiency of operation.

摘要翻译： 用于在中央处理器单元和至少一个外围单元之间进行互连的微程序控制器，用于响应于来自中央处理器单元的指令来控制数据之间的传输，通过反馈电路提供简化的比特操作，该反馈电路将要提供给 外围设备回到控制器的输入总线进行进一步处理。 以这种方式，可以通过单个微指令来实现位操作，以提供更高的速度和操作效率。

公开(公告)号：US4223381A

公开(公告)日：1980-09-16

申请号：US921075

申请日：1978-06-30

申请人： James O. Rozell ,  David W. Abmayr

发明人： James O. Rozell ,  David W. Abmayr

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/30 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F12/06 ,  G06F13/00 ,  G06F9/06

CPC分类号： G06F9/342 ,  G06F12/0623 ,  G06F9/30145 ,  G06F9/383

摘要： A selective memory addressing scheme employs a programmable read only memory (PROM) which responds to the opcode of the next instruction to be executed and supplies control information to memory module selection registers.The memory module selection registers operate in conjunction with the internal address registers to provide the necessary steering information for properly addressing the intended memory location. The PROM is programmed in accordance with the instruction set by which the processor operates and is coupled to decode the opcode contents of the instruction register that has been loaded, in a lookahead fashion, with the instruction following the instruction presently being executed by the central processing unit.The PROM has a first output that defines whether or not a second output of the PROM is to be used to select the memory module containing the operand to be referenced in the execution of the next instruction. This second output of the PROM is of a code size required to identify any one of the modules in the bank. The PROM has a third output that may be used to increment the location counter based upon the length of the next instruction. Where the second output of the PROM is not to be used to select the memory module containing the operand to be referenced, the first output of the PROM has a state such that it gates out information stored in a program status word register to identify the memory module containing the operand of the next instruction to be executed.To provide for direct CPU intervention in the execution of instructions, such as may occur in the case of an interrupt, prescribed bits of the CPU data bus may be selectively coupled to the module selection circuitry, so that the opcode-dependent operation of the PROM is bypassed and direct CPU selection within the memory bank may be achieved.

摘要翻译： 选择性存储器寻址方案采用可编程只读存储器（PROM），其响应于要执行的下一条指令的操作码，并将控制信息提供给存储器模块选择寄存器。存储器模块选择寄存器与内部地址寄存器一起操作 提供必要的指导信息，以正确地解决预期的存储位置。 PROM根据处理器操作的指令集进行编程，并且被耦合以以预先的方式将已经加载的指令寄存器的操作码内容与当前正在由中央处理执行的指令之后的指令进行解码 单元。 PROM具有第一输出，其定义是否使用PROM的第二输出来选择在执行下一条指令时包含要被引用的操作数的存储器模块。 PROM的第二个输出是识别银行中任何一个模块所需的代码大小。 PROM具有可以用于基于下一个指令的长度来增加位置计数器的第三输出。 在PROM的第二输出不被用于选择包含要被引用的操作数的存储器模块的情况下，PROM的第一输出具有这样的状态，使得它将输出存储在程序状态字寄存器中的信息来识别存储器 模块包含要执行的下一条指令的操作数。 为了提供直接CPU干预执行指令，例如在中断的情况下可能发生的CPU数据总线的指定位可以选择性地耦合到模块选择电路，使得PROM的操作码相关操作 被旁路并且可以实现存储体内的直接CPU选择。