公开(公告)号：US20130013905A1

公开(公告)日：2013-01-10

申请号：US13178338

申请日：2011-07-07

申请人： James P. Held ,  Scott H. Robinson ,  Vincent J. Zimmer

发明人： James P. Held ,  Scott H. Robinson ,  Vincent J. Zimmer

IPC分类号： G06F9/00

CPC分类号： G06F21/575 ,  G06F9/4401 ,  G06F21/64

摘要： A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.

摘要翻译： 用于BIOS闪存防护和通知的系统和方法。 包括初始化固件验证模块的处理器初始化模块可以被配置为响应于电源接通和/或复位而首先执行并且验证处理器封装中存储在非易失性存储器中的初始化固件。 初始化固件配置为验证BIOS。 如果初始化固件和/或BIOS的验证失败，则系统被配置为选择多个响应中的至少一个，包括但不限于防止BIOS执行，启动恢复，报告验证失败，停止 ，关闭和/或允许BIOS执行，以及操作系统（OS）以有限的功能模式进行引导。

公开(公告)号：US09015455B2

公开(公告)日：2015-04-21

申请号：US13178338

申请日：2011-07-07

申请人： James P. Held ,  Scott H. Robinson ,  Vincent J. Zimmer

发明人： James P. Held ,  Scott H. Robinson ,  Vincent J. Zimmer

IPC分类号： G06F9/00 ,  G06F21/57 ,  G06F9/44

CPC分类号： G06F21/575 ,  G06F9/4401 ,  G06F21/64

摘要： A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.

摘要翻译： 用于BIOS闪存防护和通知的系统和方法。 包括初始化固件验证模块的处理器初始化模块可以被配置为响应于电源接通和/或复位而首先执行并且验证处理器封装中存储在非易失性存储器中的初始化固件。 初始化固件配置为验证BIOS。 如果初始化固件和/或BIOS的验证失败，则系统被配置为选择多个响应中的至少一个，包括但不限于防止BIOS执行，启动恢复，报告验证失败，停止 ，关闭和/或允许BIOS执行，以及操作系统（OS）以有限的功能模式进行引导。

公开(公告)号：US20140013095A1

公开(公告)日：2014-01-09

申请号：US13935767

申请日：2013-07-05

申请人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

发明人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

IPC分类号： G06F9/44

CPC分类号： G06F9/4401 ,  G06F11/073 ,  G06F11/076 ,  G06F11/1092 ,  G06F21/14 ,  G06F21/572 ,  G06F21/575

摘要： In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，半导体集成代码（SIC）可由处理器制造商以二进制格式提供。 该SIC可以包括处理器制造商的平台无关代码。 这样的代码可以包括用于初始化处理器的嵌入式处理器逻辑和将处理器耦合到存储器的至少一个链路以及嵌入式存储器逻辑以初始化存储器。 描述和要求保护其他实施例。

公开(公告)号：US08296528B2

公开(公告)日：2012-10-23

申请号：US12264062

申请日：2008-11-03

申请人： Vincent J. Zimmer ,  Scott H. Robinson

发明人： Vincent J. Zimmer ,  Scott H. Robinson

IPC分类号： G06F12/08 ,  G06F12/14 ,  G06F9/24

CPC分类号： G06F12/126 ,  G06F8/60 ,  G06F12/0848 ,  G06F12/0875

摘要： Methods and systems for performing microcode patching are presented. In one embodiment, a data processing system comprises a cache memory and a processor. The cache memory comprises a plurality of cache sections. The processor sequesters one or more cache sections of the cache memory and stores processor microcode therein. In one embodiment, the processor executes the microcode in the one or more cache sections.

摘要翻译： 提出了用于执行微码修补的方法和系统。 在一个实施例中，数据处理系统包括高速缓冲存储器和处理器。 高速缓冲存储器包括多个高速缓存部分。 处理器隔离高速缓冲存储器的一个或多个高速缓存部分并在其中存储处理器微码。 在一个实施例中，处理器执行一个或多个高速缓存部分中的微代码。

公开(公告)号：US08522066B2

公开(公告)日：2013-08-27

申请号：US12823343

申请日：2010-06-25

申请人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

发明人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

IPC分类号： G06F1/10 ,  G06F1/12

CPC分类号： G06F9/4401 ,  G06F11/073 ,  G06F11/076 ,  G06F11/1092 ,  G06F21/14 ,  G06F21/572 ,  G06F21/575

摘要： In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

公开(公告)号：US20110320798A1

公开(公告)日：2011-12-29

申请号：US12823343

申请日：2010-06-25

申请人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

发明人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

IPC分类号： G06F9/24 ,  G06F9/00

CPC分类号： G06F9/4401 ,  G06F11/073 ,  G06F11/076 ,  G06F11/1092 ,  G06F21/14 ,  G06F21/572 ,  G06F21/575

摘要： In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，半导体集成代码（SIC）可由处理器制造商以二进制格式提供。 该SIC可以包括处理器制造商的平台无关代码。 这样的代码可以包括用于初始化处理器的嵌入式处理器逻辑和将处理器耦合到存储器的至少一个链路以及嵌入式存储器逻辑以初始化存储器。 描述和要求保护其他实施例。

公开(公告)号：US20100115202A1

公开(公告)日：2010-05-06

申请号：US12264062

申请日：2008-11-03

申请人： Vincent J. Zimmer ,  Scott H. Robinson

发明人： Vincent J. Zimmer ,  Scott H. Robinson

IPC分类号： G06F12/08

CPC分类号： G06F12/126 ,  G06F8/60 ,  G06F12/0848 ,  G06F12/0875

摘要： Methods and systems for performing microcode patching are presented. In one embodiment, a data processing system comprises a cache memory and a processor. The cache memory comprises a plurality of cache sections. The processor sequesters one or more cache sections of the cache memory and stores processor microcode therein. In one embodiment, the processor executes the microcode in the one or more cache sections.

摘要翻译： 提出了用于执行微码修补的方法和系统。 在一个实施例中，数据处理系统包括高速缓冲存储器和处理器。 高速缓冲存储器包括多个高速缓存部分。 处理器隔离高速缓冲存储器的一个或多个高速缓存部分并在其中存储处理器微码。 在一个实施例中，处理器执行一个或多个高速缓存部分中的微代码。

公开(公告)号：US09958926B2

公开(公告)日：2018-05-01

申请号：US13976903

申请日：2011-12-13

申请人： Leena K. Puthiyedath ,  Raj K. Ramanujan ,  Michael Rothman ,  Blaise Fanning ,  Vincent J. Zimmer

发明人： Leena K. Puthiyedath ,  Raj K. Ramanujan ,  Michael Rothman ,  Blaise Fanning ,  Vincent J. Zimmer

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

公开(公告)号：US20170185207A1

公开(公告)日：2017-06-29

申请号：US14998314

申请日：2015-12-26

申请人： Rajesh Poornachandran ,  Vincent J. Zimmer ,  Nicholas J. Adams ,  Nithyananda S. Jeganathan ,  Gunner D. Danneels

发明人： Rajesh Poornachandran ,  Vincent J. Zimmer ,  Nicholas J. Adams ,  Nithyananda S. Jeganathan ,  Gunner D. Danneels

IPC分类号： G06F3/041 ,  G06F1/16

CPC分类号： G06F3/0416 ,  G06F1/1652 ,  G06F3/0412 ,  G06F9/44505

摘要： Technologies for dynamic display include a mobile compute device that comprises a display transformable between at least two different physical topologies. The mobile compute device determines a current physical topology of the display and retrieves a policy based on the determined current physical topology. The policy identifies a corresponding action to occur in response to each of one or more user inputs to the mobile compute device while the display has the current physical topology. The mobile compute device processes a user input based on the retrieved policy.

公开(公告)号：US20170177395A1

公开(公告)日：2017-06-22

申请号：US14976936

申请日：2015-12-21

申请人： Mingqiu Sun ,  Vincent J. Zimmer ,  Rajesh Poornachandran ,  Gopinatth Selvaraje

发明人： Mingqiu Sun ,  Vincent J. Zimmer ,  Rajesh Poornachandran ,  Gopinatth Selvaraje

IPC分类号： G06F9/455 ,  G06F9/50

CPC分类号： G06F9/45558 ,  G06F9/5038 ,  G06F2009/4557 ,  G06F2009/45575 ,  G06F2009/45587

摘要： A system on a chip (SoC) may comprise at least one processor with at least one core and a storage device comprising a first system virtual machine configured to be executed on the at least one processor. The storage device may comprise a second system virtual machine configured to be executed by the at least one processor. The second system virtual machine may include at least one process virtual machine; a modem configured as one of the at least one process virtual machine; and a real-time operating system (RTOS) to schedule execution of the at least one process virtual machine on the at least one processor.