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    System and method for adaptive buffer allocation in a memory device interface
    1.
    发明授权
    System and method for adaptive buffer allocation in a memory device interface 有权
    用于存储设备接口中自适应缓冲区分配的系统和方法

    公开(公告)号：US07451254B2

    公开(公告)日：2008-11-11

    申请号：US10631160

    申请日：2003-07-31

    申请人： James R. Peterson ,  Matthew B. Lovell ,  Darel N. Emmot

    发明人： James R. Peterson ,  Matthew B. Lovell ,  Darel N. Emmot

    IPC分类号： G06F13/12

    CPC分类号： G06F13/4059

    摘要： A method for allocating buffer capacity includes determining at least one characteristic of a first input/output (I/O) device that is coupled to a memory device interface, the memory device interface being configured to enable data transfers between the I/O device and a memory device, and buffering data corresponding to the first I/O device in a first portion of a buffer of the memory device interface, a size of the first portion being responsive to the at least one characteristic of the first I/O device.

    摘要翻译： 用于分配缓冲器容量的方法包括确定耦合到存储器设备接口的第一输入/输出（I / O）设备的至少一个特性，所述存储器设备接口被配置为使得能够在所述I / O设备和 存储器设备，以及缓冲与存储器设备接口的缓冲器的第一部分中的第一I / O设备相对应的数据，第一部分的大小响应于第一I / O设备的至少一个特性。

    Method and apparatus for appending memory commands during a direct memory access operation
    3.
    发明授权
    Method and apparatus for appending memory commands during a direct memory access operation 有权
    在直接存储器访问操作期间附加存储器命令的方法和装置

    公开(公告)号：US06678755B1

    公开(公告)日：2004-01-13

    申请号：US09608544

    申请日：2000-06-30

    申请人： James R. Peterson ,  Aaftab Munshi ,  Mohammed Sriti

    发明人： James R. Peterson ,  Aaftab Munshi ,  Mohammed Sriti

    IPC分类号： G06F1314

    CPC分类号： G06F13/28

    摘要： A direct memory access (DMA) controller for controlling memory access operations in a memory. During a memory access operation, the DMA controller executes a chain of DMA commands stored in a memory and having a respective address. The DMA controller can enter a self-linking mode where additional DMA commands can be appended to the end of the command chain without terminating the memory access operation, regardless of whether the last DMA command of the command chain has been executed by the DMA controller. The self-linking mode is entered when a link-address provided by the last DMA command matches a code. The code to cause the DMA controller to enter the self-linking mode may be a link address which points to the last executed DMA command, or alternatively, a predetermined bit pattern. The DMA controller exits the self-linking command and continues the memory access operation upon detecting a new link address for a new DMA command that is to be appended to the command chain. The new link address may be detected by having the DMA controller periodically check the link address of the last executed DMA command.

    摘要翻译： 用于控制存储器中的存储器访问操作的直接存储器访问（DMA）控制器。 在存储器访问操作期间，DMA控制器执行存储在存储器中并具有相应地址的一系列DMA命令。 DMA控制器可以进入自链接模式，其中附加的DMA命令可以附加到命令链的末尾而不终止存储器访问操作，而不管命令链的最后一个DMA命令是否由DMA控制器执行。 当最后一个DMA命令提供的链接地址匹配一个代码时，输​​入自链接模式。 导致DMA控制器进入自链接模式的代码可以是指向最后执行的DMA命令的链接地址，或者备选地是预定位模式。 DMA控制器退出自链接命令，并在检测到要附加到命令链的新DMA命令的新链接地址时继续存储器访问操作。 可以通过使DMA控制器周期性地检查最后执行的DMA命令的链路地址来检测新的链路地址。

    Memory system having programmable multiple and continuous memory regions and method of use thereof
    4.
    发明授权
    Memory system having programmable multiple and continuous memory regions and method of use thereof 有权

    公开(公告)号：US06646646B2

    公开(公告)日：2003-11-11

    申请号：US09737231

    申请日：2000-12-13

    申请人： James R. Peterson ,  William Radke

    发明人： James R. Peterson ,  William Radke

    IPC分类号： G06F1202

    CPC分类号： G09G5/363 ,  G06F12/0292 ,  G09G2360/12

    摘要： A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region. The memory controller is adapted to access the first addressable memory region in response to receiving a memory address for a location within the first portions of the first and second memory spaces and to access the second addressable memory region in response to receiving a memory address for a location within the second portions of the first and second memory spaces.

    Thermal slider level transfer curve tester for testing recording heads
    5.
    发明授权
    Thermal slider level transfer curve tester for testing recording heads 失效
    热敏滑块级传输曲线测试仪用于测试记录头

    公开(公告)号：US06486660B1

    公开(公告)日：2002-11-26

    申请号：US09814433

    申请日：2001-03-21

    申请人： Todd A. Luse ,  James R. Peterson ,  Thien T. Tu

    发明人： Todd A. Luse ,  James R. Peterson ,  Thien T. Tu

    IPC分类号： G01R3312

    CPC分类号： G11B5/455 ,  G11B33/10 ,  G11B33/14 ,  G11B2005/0013 ,  G11B2005/0016

    摘要： A head testing apparatus is provided for testing a data recording head. The apparatus includes a test volume, a magnetic field source, a holder and a thermoelectric source. The test volume is adapted to receive the head, and the magnetic field source is positioned to generate a magnetic field within the test volume. The holder is adapted to hold the head and position the head within the test volume. The thermoelectric source is positioned to contact the head when the head is positioned within the test volume by the holder.

    摘要翻译： 提供头测试装置用于测试数据记录头。 该装置包括测试体积，磁场源，保持器和热电源。 测试体积适于接收头部，磁场源被定位成在测试体积内产生磁场。 保持器适于保持头部并将头部定位在测试体积内。 当头部由保持器定位在测试体积内时，热电源被定位成接触头部。

    Quick change stacked tube feeder
    6.
    发明授权
    Quick change stacked tube feeder 失效
    快速更换堆叠式送料机

    公开(公告)号：US6126376A

    公开(公告)日：2000-10-03

    申请号：US16290

    申请日：1998-01-30

    申请人： James R. Peterson

    发明人： James R. Peterson

    IPC分类号： H05K13/02 ,  B65B69/00

    CPC分类号： H05K13/021 ,  Y10T29/53478

    摘要： The invention is a stacked tube component feeder with changeable parts to accommodate different size components. A feed station, including a channel, is mounted on a base. The feed station includes a slot for holding component tubes. A changeable component track is mounted in the channel, and a singulator is mounted on the component track to prevent the feeding of more than one component at a time to a changeable component nest. A removable nest is mounted on the base for receiving components from the removable component track, and transports the component between first and second positions on the base.

    摘要翻译： 本发明是一种具有可变部件以容纳不同尺寸部件的堆叠管部件进料器。 包括通道的进料站安装在基座上。 进料站包括用于保持组分管的槽。 可变组件轨道安装在通道中，并且分离器安装在组件轨道上，以防止一次将多于一个组件进给到可更换组件嵌套。 可移动的嵌套安装在基座上用于从可拆卸的部件轨道接收组件，并且在基座上的第一和第二位置之间传送部件。

    Method of making ventilation apparatus
    9.
    发明授权
    Method of making ventilation apparatus 失效
    通风装置的制作方法

    公开(公告)号：US4461066A

    公开(公告)日：1984-07-24

    申请号：US444650

    申请日：1982-11-26

    申请人： James R. Peterson

    发明人： James R. Peterson

    IPC分类号： B21D53/00 ,  F24F7/02 ,  B21D39/00 ,  B23P11/00

    CPC分类号： F24F7/02 ,  B21D53/00 ,  Y10T29/49879 ,  Y10T29/49917 ,  Y10T29/49927

    摘要： A unitary, metal vent apparatus for securement to the roof of a building. The apparatus includes a one-piece hollow first member having a series of vent holes near its top portion. The apparatus also includes a one-piece second member which forms a concentric cap for the first member and which protects the upper portion of the first member from the elements, but does not impair or contact the vent holes. Preferably, the cap is spun onto the first member for rigid securement thereto.

    摘要翻译： 用于固定在建筑物屋顶的整体式金属通风装置。 该装置包括在其顶部附近具有一系列通气孔的一件式中空的第一构件。 该装置还包括一体的第二构件，其形成用于第一构件的同心帽并且保护第一构件的上部免受元件的影响，但不损害或接触通气孔。 优选地，将盖旋转到第一构件上用于刚性固定到其上。

    System and method for converting a non-interlaced video signal into an interlaced video signal
    10.
    发明授权
    System and method for converting a non-interlaced video signal into an interlaced video signal 失效
    用于将非隔行扫描视频信号转换为隔行视频信号的系统和方法

    公开(公告)号：US4386367A

    公开(公告)日：1983-05-31

    申请号：US277788

    申请日：1981-06-26

    申请人： James R. Peterson ,  Douglas J. Doornink

    发明人： James R. Peterson ,  Douglas J. Doornink

    IPC分类号： G09G5/00 ,  H04N7/01 ,  H04N5/02

    CPC分类号： H04N7/0105

    摘要： A system and method for receiving an input bit stream defining a non-interlaced video image and for producing concurrently an output bit stream defining an interlaced representation of such image. Intermediate storage of every other input raster line in a first-in/first-out oriented memory permits the output of the interlaced signal to be interleaved with the receipt of the non-interlaced input, and the interleaving of the input and output operations permits the use of a memory module having a capacity less than that required to store a complete raster line of input information. Provision is also made for synchronizing the output operation to U.S. or European standards.

    摘要翻译： 一种用于接收定义非间行视频图像的输入比特流并同时产生定义这种图像的隔行扫描表示的输出比特流的系统和方法。 在先进先出的存储器中的每个其他输入光栅线的中间存储允许隔行信号的输出与非隔行输入的接收交错，并且输入和输出操作的交错允许 使用容量小于存储输入信息的完整光栅线所需容量的存储器模块。 还规定了输出操作与美国或欧洲标准的同步。