公开(公告)号：US5381543A

公开(公告)日：1995-01-10

申请号：US206563

申请日：1994-03-03

申请人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

发明人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

IPC分类号： G06F13/42 ,  G06F1/06

CPC分类号： G06F13/4217

摘要： The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e. the address status signal) generated by the CPU. The ADS and RDY signals must be modified in a first way if the CPU calls for a memory cycle at the beginning of a bus cycle and in a second way if the CPU calls for a memory cycle in the middle of a CPU cycle. The use of a CPU clock speed doubler in combination with a write-back cache achieves truly synergistic increases in system speed.

摘要翻译： 本发明提供了一种用于在存储器总线的周期速度的多频道处在单个微处理器中操作CPU的装置。 利用本发明，提供了第一和第二定时信号。 第二定时信号的频率是第一定时信号的频率的倍数。 将第二或快速定时信号提供给CPU，并将第一或更慢的定时信号提供给存储器子系统。 总线接口单元插在CPU和存储器总线之间。 该总线接口单元从存储器子系统接收RDY信号（即就绪信号），并在将其提供给CPU之前对其进行修改。 来自存储器子系统的“就绪”信号在每个总线周期的很大部分处于未定义状态。 由于在每个存储器访问期间至少发生两个CPU周期，因此总线接口单元必须确保CPU不会误解来自存储器子系统的就绪信号。 总线接口单元还必须修改由CPU产生的ADS信号（即地址状态信号）。 如果CPU在总线周期开始时要求存储器周期，并且如果CPU在CPU周期中要求存储器周期，则ADS和RDY信号必须以第一种方式进行修改。 使用CPU时钟速度倍增器与回写缓存相结合，实现了系统速度的真正协同增长。

公开(公告)号：US5325516A

公开(公告)日：1994-06-28

申请号：US848544

申请日：1992-03-09

申请人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

发明人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4217

摘要： The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e. the address status signal) generated by the CPU. The ADS and RDY signals must be modified in a first way if the CPU calls for a memory cycle at the beginning of a bus cycle and in a second way if the CPU calls for a memory cycle in the middle of a CPU cycle. The use of a CPU clock speed doubler in combination with a write-back cache achieves truly synergistic increases in system speed.

摘要翻译： 本发明提供了一种用于在存储器总线的周期速度的多频道处在单个微处理器中操作CPU的装置。 利用本发明，提供了第一和第二定时信号。 第二定时信号的频率是第一定时信号的频率的倍数。 将第二或快速定时信号提供给CPU，并将第一或更慢的定时信号提供给存储器子系统。 总线接口单元插在CPU和存储器总线之间。 该总线接口单元从存储器子系统接收RDY信号（即就绪信号），并在将其提供给CPU之前对其进行修改。 来自存储器子系统的“就绪”信号在每个总线周期的很大部分处于未定义状态。 由于在每个存储器访问期间至少发生两个CPU周期，因此总线接口单元必须确保CPU不会误解来自存储器子系统的就绪信号。 总线接口单元还必须修改由CPU产生的ADS信号（即地址状态信号）。 如果CPU在总线周期开始时要求存储器周期，并且如果CPU在CPU周期中要求存储器周期，则ADS和RDY信号必须以第一种方式进行修改。 使用CPU时钟速度倍增器与回写缓存相结合，实现了系统速度的真正协同增长。

公开(公告)号：US5276825A

公开(公告)日：1994-01-04

申请号：US667942

申请日：1991-03-12

申请人： James S. Blomgren ,  Tuan Luong ,  Winnie Yu

发明人： James S. Blomgren ,  Tuan Luong ,  Winnie Yu

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/324 ,  G06F9/322 ,  G06F9/3804

摘要： A method and apparatus for performing a fast jump address calculation is disclosed. A field from the instruction is provided to an adder, on the assumption that it is the displacement value, without actually determining whether it is a displacement value. A fixed instruction length is also provided to the adder, on the assumption that the instruction will have that length. Finally, the current instruction address bits from the program counter are provided to the adder. These are added together to provide a jump address.

摘要翻译： 公开了一种执行快速跳转地址计算的方法和装置。 假定它是位移值，而不实际确定它是否为位移值，则将来自指令的场提供给加法器。 假设指令将具有该长度，也向加法器提供固定的指令长度。 最后，将来自程序计数器的当前指令地址位提供给加法器。 这些被添加在一起以提供跳转地址。

公开(公告)号：US5313606A

公开(公告)日：1994-05-17

申请号：US642977

申请日：1991-01-17

申请人： Tuan Luong ,  James S. Blomgren ,  Winnie Yu

发明人： Tuan Luong ,  James S. Blomgren ,  Winnie Yu

IPC分类号： G06F12/14

CPC分类号： G06F12/1441

摘要： An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception occurs.

摘要翻译： 用于检查分段违例的改进系统计数在控制传送操作之后从控制段访问的总字节数。 如果计数指示从控制段外部取出指令的一部分，则发生极限异常。