INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE
    1.
    发明申请
    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE 有权
    使用3字节ESCAPE操作码的指令集扩展

    公开(公告)号:US20130219152A1

    公开(公告)日:2013-08-22

    申请号:US13844471

    申请日:2013-03-15

    IPC分类号: G06F9/30

    摘要: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

    摘要翻译: 公开了用于对可变长度指令集中的指令进行解码的方法,装置和系统。 该指令是一组新的指令之一,它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令,可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度,其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例,在不评估指令特定操作码的情况下确定新指令之一的长度。

    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE
    4.
    发明申请
    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE 有权
    使用3字节ESCAPE操作码的指令集扩展

    公开(公告)号:US20120173852A1

    公开(公告)日:2012-07-05

    申请号:US13417241

    申请日:2012-03-10

    IPC分类号: G06F9/30

    摘要: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

    摘要翻译: 公开了用于对可变长度指令集中的指令进行解码的方法,装置和系统。 该指令是一组新的指令之一,它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令,可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度,其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例,在不评估指令特定操作码的情况下确定新指令之一的长度。

    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE
    6.
    发明申请
    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE 有权
    使用3字节ESCAPE操作码的指令集扩展

    公开(公告)号:US20080148019A1

    公开(公告)日:2008-06-19

    申请号:US12039719

    申请日:2008-02-28

    IPC分类号: G06F9/30

    摘要: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

    摘要翻译: 公开了用于对可变长度指令集中的指令进行解码的方法,装置和系统。 该指令是一组新的指令之一,它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令,可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度,其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例,在不评估指令特定操作码的情况下确定新指令之一的长度。

    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE
    7.
    发明申请
    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE 有权
    使用3字节ESCAPE操作码的指令集扩展

    公开(公告)号:US20110173418A1

    公开(公告)日:2011-07-14

    申请号:US13070908

    申请日:2011-03-24

    IPC分类号: G06F9/30

    摘要: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

    摘要翻译: 公开了用于对可变长度指令集中的指令进行解码的方法,装置和系统。 该指令是一组新的指令之一,它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令,可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度,其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例,在不评估指令特定操作码的情况下确定新指令之一的长度。

    Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks

    公开(公告)号:US10157061B2

    公开(公告)日:2018-12-18

    申请号:US13994060

    申请日:2011-12-22

    IPC分类号: G06F9/30

    摘要: According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.