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1.发明申请INSTRUCTIONS FOR STORING IN GENERAL PURPOSE REGISTERS ONE OF TWO SCALAR CONSTANTS BASED ON THE CONTENTS OF VECTOR WRITE MASKS 审中-公开用于存储一般用途注册表的指令基于矢量写掩码内容的两个标量常数之一公开(公告)号：US20140297991A1
公开(公告)日：2014-10-02
申请号：US13994060
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30029 , G06F9/30054
摘要： According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.
摘要翻译： 根据一个实施例，获取指令的发生。 指令的格式仅指定单个向量写入掩码寄存器的源操作数，并将其指定为单个通用寄存器。 此外，指令的格式包括其内容选择单向量写入掩码寄存器的第一字段，并且包括其内容选择单个通用寄存器的第二字段。 源操作数是包括对应于架构向量寄存器内的不同多位数据元素位置的多个一位向量写入掩码元素的写入掩码。 该方法还包括：响应于执行单个指令的单次发生，将数据存储在单个通用寄存器中，使得其内容基于第一或第二标量常数是否基于第 源操作数全部为零。
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公开(公告)号：US10157061B2
公开(公告)日：2018-12-18
申请号：US13994060
申请日：2011-12-22
IPC分类号： G06F9/30
摘要： According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.
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公开(公告)号：US20160041827A1
公开(公告)日：2016-02-11
申请号：US13995944
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method is described that includes fetching an instruction and decoding the instruction. The method further includes fetching a first mask vector from a first mask register space location identified by the instruction. The method further includes fetching a second mask vector from a second mask register space location identified by the instruction. The method also includes executing the instruction by merging the first and second mask vectors into a single data structure and causing the single data structure to be written into a memory location identified by the instruction.
摘要翻译： 描述了一种包括获取指令并解码指令的方法。 该方法还包括从由该指令识别的第一屏蔽寄存器空间位置获取第一屏蔽矢量。 该方法还包括从由该指令识别的第二屏蔽寄存器空间位置获取第二屏蔽矢量。 该方法还包括通过将第一和第二屏蔽矢量合并为单个数据结构并使单个数据结构被写入由该指令识别的存储器位置来执行该指令。
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公开(公告)号：US09766886B2
公开(公告)日：2017-09-19
申请号：US13977736
申请日：2011-12-16
IPC分类号： G06F9/302 , G06F9/315 , G06F17/17 , G09G5/00 , G06F15/76 , G06F9/30 , G06F9/38 , G06T3/40 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30007 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30109 , G06F9/30145 , G06F9/3016 , G06F9/30185 , G06F9/3836 , G06F15/8053 , G06F17/17 , G06T3/4007
摘要： Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.
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公开(公告)号：US09733935B2
公开(公告)日：2017-08-15
申请号：US13976404
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.
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公开(公告)号：US08972698B2
公开(公告)日：2015-03-03
申请号：US12976616
申请日：2010-12-22
申请人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
发明人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译： 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。
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公开(公告)号：US20140164705A1
公开(公告)日：2014-06-12
申请号：US13976429
申请日：2011-12-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30047 , G06F12/0811 , G06F12/0862
摘要： A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.
摘要翻译： 描述由处理器执行的方法。 该方法包括执行指令。 该指令具有作为操作数的地址。 指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。 响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。 高速缓存行不在处理器的高速缓存中。 所有权请求也表示高速缓存行不被发送到处理器。
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公开(公告)号：US20120166761A1
公开(公告)日：2012-06-28
申请号：US12976616
申请日：2010-12-22
申请人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
发明人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译： 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。
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公开(公告)号：US09792115B2
公开(公告)日：2017-10-17
申请号：US13976997
申请日：2011-12-23
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
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公开(公告)号：US20140052968A1
公开(公告)日：2014-02-20
申请号：US13976404
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.
摘要翻译： 描述了处理指令的方法，其包括获取和解码指令。 该指令具有单独的目标地址，第一个操作数源地址和第二个操作数源地址组件。 第一个操作数源地址标识掩码寄存器空间中第一个掩码模式的位置。 第二操作数源地址在掩码寄存器空间中标识第二掩码图案的位置。 该方法还包括从掩模寄存器空间获取第一掩模图案; 从掩模寄存器空间中取出第二掩模图案; 将第一和第二掩模图案合并成合并的掩模图案; 以及将合并的掩模图案存储在由目的地地址识别的存储位置。
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