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1.发明申请INSTRUCTIONS FOR STORING IN GENERAL PURPOSE REGISTERS ONE OF TWO SCALAR CONSTANTS BASED ON THE CONTENTS OF VECTOR WRITE MASKS 审中-公开用于存储一般用途注册表的指令基于矢量写掩码内容的两个标量常数之一公开(公告)号：US20140297991A1
公开(公告)日：2014-10-02
申请号：US13994060
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30029 , G06F9/30054
摘要： According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.
摘要翻译： 根据一个实施例，获取指令的发生。 指令的格式仅指定单个向量写入掩码寄存器的源操作数，并将其指定为单个通用寄存器。 此外，指令的格式包括其内容选择单向量写入掩码寄存器的第一字段，并且包括其内容选择单个通用寄存器的第二字段。 源操作数是包括对应于架构向量寄存器内的不同多位数据元素位置的多个一位向量写入掩码元素的写入掩码。 该方法还包括：响应于执行单个指令的单次发生，将数据存储在单个通用寄存器中，使得其内容基于第一或第二标量常数是否基于第 源操作数全部为零。
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公开(公告)号：US10157061B2
公开(公告)日：2018-12-18
申请号：US13994060
申请日：2011-12-22
IPC分类号： G06F9/30
摘要： According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.
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公开(公告)号：US20160041827A1
公开(公告)日：2016-02-11
申请号：US13995944
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method is described that includes fetching an instruction and decoding the instruction. The method further includes fetching a first mask vector from a first mask register space location identified by the instruction. The method further includes fetching a second mask vector from a second mask register space location identified by the instruction. The method also includes executing the instruction by merging the first and second mask vectors into a single data structure and causing the single data structure to be written into a memory location identified by the instruction.
摘要翻译： 描述了一种包括获取指令并解码指令的方法。 该方法还包括从由该指令识别的第一屏蔽寄存器空间位置获取第一屏蔽矢量。 该方法还包括从由该指令识别的第二屏蔽寄存器空间位置获取第二屏蔽矢量。 该方法还包括通过将第一和第二屏蔽矢量合并为单个数据结构并使单个数据结构被写入由该指令识别的存储器位置来执行该指令。
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公开(公告)号：US10203954B2
公开(公告)日：2019-02-12
申请号：US13977732
申请日：2011-11-25
摘要： Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.
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公开(公告)号：US10037205B2
公开(公告)日：2018-07-31
申请号：US13977734
申请日：2011-12-23
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/3887
摘要： Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.
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公开(公告)号：US09489196B2
公开(公告)日：2016-11-08
申请号：US13997998
申请日：2011-12-23
申请人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
发明人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
CPC分类号： G06F9/3013 , G06F7/764 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30036
摘要： A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.
摘要翻译： 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。
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公开(公告)号：US09354877B2
公开(公告)日：2016-05-31
申请号：US13992709
申请日：2011-12-23
CPC分类号： G06F9/30018 , G06F9/30025 , G06F9/30098 , G06F9/30181
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode are described.
摘要翻译： 描述了在计算机处理器中执行屏蔽位压缩的系统，装置和方法的实施例，其响应于包括源写入寄存器操作数，目的地写入寄存器操作数和操作码的单个掩码位压缩指令。
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8.发明申请INSTRUCTION AND LOGIC TO PROVIDE CONVERSIONS BETWEEN A MASK REGISTER AND A GENERAL PURPOSE REGISTER OR MEMORY 审中-公开指令和逻辑提供掩码寄存器与一般用途寄存器或存储器之间的转换公开(公告)号：US20150113246A1
公开(公告)日：2015-04-23
申请号：US13977732
申请日：2011-11-25
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/30145 , G06F9/30185 , G06F9/3826 , G06F9/3877
摘要： Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.
摘要翻译： 指令和逻辑在掩码寄存器和通用寄存器或存储器之间提供转换。 一些实施例，响应于指定目的地操作数，对应于多个掩码数据字段的掩码长度和源操作数的指令; 从源操作数的数据字段读取值，该数据字段对应于指定的掩码长度，并存储到由指令指定的目标操作数中的相应数据字段，其中源操作数或目标操作数中的一个是掩码寄存器。 指示屏蔽矢量元素的值可以被存储到目的地操作数中除了对应于指定掩码长度的数据字段的数目之外的任何数据字段。 对于一些实施例，源或目的地操作数中的另一个可以是通用寄存器或存储器位置。
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公开(公告)号：US20140019732A1
公开(公告)日：2014-01-16
申请号：US13992709
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30025 , G06F9/30098 , G06F9/30181
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode are described.
摘要翻译： 描述了在计算机处理器中执行屏蔽位压缩的系统，装置和方法的实施例，其响应于包括源写入寄存器操作数，目的地写入寄存器操作数和操作码的单个掩码位压缩指令。
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公开(公告)号：US20130283021A1
公开(公告)日：2013-10-24
申请号：US13976992
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F9/30167 , G06F9/3802
摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.
摘要翻译： 描述了具有执行第一，第二，第三和第四指令的指令执行逻辑电路的装置。 第一指令和第二指令都将第一组输入向量元素插入到相应的第一和第二合成向量的多个第一非重叠部分之一中。 第一组具有第一位宽度。 多个第一非重叠部分中的每一个具有与第一组相同的位宽度。 第三指令和第四指令都将第二组输入矢量元素插入相应的第三和第四合成矢量的多个第二非重叠部分中的一个。 第二组具有大于所述第一位宽度的第二位宽度。 多个第二非重叠部分中的每一个具有与第二组相同的位宽度。 该装置还包括掩蔽层电路，以第一合成矢量粒度掩蔽第一和第三指令，并以第二合成向量粒度掩蔽第二和第四指令。
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