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21 条记录 (耗时 0.051 秒)

    Method and apparatus for testing interconnect bridging faults in an FPGA
    8.
    发明授权
    Method and apparatus for testing interconnect bridging faults in an FPGA 失效
    用于测试FPGA中互连桥接故障的方法和装置

    公开(公告)号：US07103813B1

    公开(公告)日：2006-09-05

    申请号：US10703400

    申请日：2003-11-06

    申请人： Paul Tracy ,  Anthony Pang ,  Andy Lee ,  Adam Wright ,  Rahul Saini

    发明人： Paul Tracy ,  Anthony Pang ,  Andy Lee ,  Adam Wright ,  Rahul Saini

    IPC分类号： G01R31/02 ,  G06F11/267

    CPC分类号： G01R31/31717 ,  G01R31/318519

    摘要： A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.

    摘要翻译： 桥接故障检测系统允许使用低数量的测试配置进行大量的测试覆盖。 桥接故障检测系统自动创建最佳测试配置和测试向量，而不需要精确的布局信息，并且适用于复杂的可编程设备架构。 测试人员可以指定一个精确的测试覆盖水平以优化测试处理。 具有互连偏置电路的可编程器件减少测试配置的数量，从而减少测试桥接故障所需的时间。 互连偏置电路在配置中对未使用的线路提供显式测试控制，驱动它们高和低以在每条线路与其所有可能的邻居之间完成测试覆盖。 桥接故障检测系统通过可编程连接平衡可用数量的控制测试点与拼接在一起的互连段的数量，以最大化每个配置的待测线路。

    Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method
    9.
    发明授权
    Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method 有权
    可编程逻辑器件具有可修复电路阵列内的不可修复电路区域和相关配置硬件和方法

    公开(公告)号：US07215140B1

    公开(公告)日：2007-05-08

    申请号：US10452673

    申请日：2003-05-30

    申请人： Rahul Saini ,  Andy Lee ,  Ninh Ngo

    发明人： Rahul Saini ,  Andy Lee ,  Ninh Ngo

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17764

    摘要： An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.

    摘要翻译： 本发明的一个实施例提供一种可编程逻辑器件（“PLD”），其包括一个或多个可修复逻辑阵列区域内的一个或多个专用电路块。 本发明的方面提供用于在PLD的规则和测试编程序列期间控制专用块区域和完全可修复的逻辑阵列区域的正常和冗余模式中的编程数据的移位的电路和方法。 其他方面提供用于在正常模式和冗余模式中的专用块和可修复逻辑阵列区之间的接口路由的电路和方法。 还公开了各种其它方面。