公开(公告)号：US06660664B1

公开(公告)日：2003-12-09

申请号：US09541091

申请日：2000-03-31

申请人： James W. Adkisson ,  Arne W. Ballantine ,  Matthew D. Gallagher ,  Peter J. Geiss ,  Jeffrey D. Gilbert ,  Shwu-Jen Jeng ,  Donna K. Johnson ,  Robb A. Johnson ,  Glen L. Miles ,  Kirk D. Peterson ,  James J. Toomey ,  Tina Wagner

发明人： James W. Adkisson ,  Arne W. Ballantine ,  Matthew D. Gallagher ,  Peter J. Geiss ,  Jeffrey D. Gilbert ,  Shwu-Jen Jeng ,  Donna K. Johnson ,  Robb A. Johnson ,  Glen L. Miles ,  Kirk D. Peterson ,  James J. Toomey ,  Tina Wagner

IPC分类号： H01L2131

CPC分类号： H01L28/20 ,  H01L21/3185

摘要： A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

摘要翻译： 一种在半导体衬底上形成氮化物膜的方法，包括将衬底的表面暴露于快速热处理以形成氮化物膜。

公开(公告)号：US06900519B2

公开(公告)日：2005-05-31

申请号：US10865138

申请日：2004-06-10

申请人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L27/082

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

公开(公告)号：US06869854B2

公开(公告)日：2005-03-22

申请号：US10064476

申请日：2002-07-18

申请人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L23/62

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

摘要翻译： 本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。 本发明的优选实施例通过提供降低的基极电阻来提供改进的高速性能。 优选的设计通过将掺杂剂从掺杂剂源层扩散到外部碱性区域中形成外部碱基。 掺杂剂的这种扩散形成至少一部分外在碱。 特别地，通过扩散形成与本征基区相邻的部分。 该解决方案避免了植入外在基础的传统解决方案所引起的问题。 具体地说，通过扩散形成外部基体的至少一部分，能够使基部区域的损伤问题最小化。 这种降低的损伤增强了掺杂剂扩散到本征基质中。 另外，形成的外部基极可以具有改善的电阻，导致双极器件的最大频率改善。 另外，外部基座可以通过降低制造复杂性的自对准制造工艺来形成。

公开(公告)号：US06600199B2

公开(公告)日：2003-07-29

申请号：US09752061

申请日：2000-12-29

申请人： Steven H. Voldman ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge

发明人： Steven H. Voldman ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge

IPC分类号： H01L2976

CPC分类号： H01L29/66287 ,  H01L21/761 ,  H01L21/8249

摘要： The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.