公开(公告)号：US07194706B2

公开(公告)日：2007-03-20

申请号：US10710642

申请日：2004-07-27

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

公开(公告)号：US07089514B2

公开(公告)日：2006-08-08

申请号：US10710879

申请日：2004-08-10

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G01R31/318342

摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

摘要翻译： 一种半导体芯片缺陷诊断方法。 该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

公开(公告)号：US06998866B1

公开(公告)日：2006-02-14

申请号：US10710640

申请日：2004-07-27

申请人： Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak

发明人： Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  G01R31/31855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.

摘要翻译： 用于监测集成电路芯片中的缺陷的电路和方法。 所述电路包括缺陷监测部分和感测元件部分，所述缺陷监测部分耦合到布置在链中的感测元件的输入或耦合在感测元件和链的形成部分之间。

公开(公告)号：US07620931B2

公开(公告)日：2009-11-17

申请号：US11859890

申请日：2007-09-24

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US07323278B2

公开(公告)日：2008-01-29

申请号：US11687731

申请日：2007-03-19

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G03F9/00 ,  G03C5/00

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US07240322B2

公开(公告)日：2007-07-03

申请号：US10907494

申请日：2005-04-04

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US07005874B2

公开(公告)日：2006-02-28

申请号：US10710222

申请日：2004-06-28

申请人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

发明人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G01R31/02

CPC分类号： G01R31/31727 ,  G01R31/025 ,  G01R31/30 ,  G01R31/31725

摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

摘要翻译： 公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。 屏蔽与时钟信号接线相邻，接地线将屏蔽接地。 屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。 本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

公开(公告)号：US07239167B2

公开(公告)日：2007-07-03

申请号：US11382601

申请日：2006-05-10

申请人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

发明人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G01R31/02

CPC分类号： G01R31/31727 ,  G01R31/025 ,  G01R31/30 ,  G01R31/31725

摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

摘要翻译： 公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。 屏蔽与时钟信号接线相邻，接地线将屏蔽接地。 屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。 本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

公开(公告)号：US07088124B2

公开(公告)日：2006-08-08

申请号：US11280008

申请日：2005-11-16

申请人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

发明人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G01R31/02

CPC分类号： G01R31/31727 ,  G01R31/025 ,  G01R31/30 ,  G01R31/31725

摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

公开(公告)号：US07078248B2

公开(公告)日：2006-07-18

申请号：US10710114

申请日：2004-06-18

申请人： John M. Cohn ,  Leah Marie P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

发明人： John M. Cohn ,  Leah Marie P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： H01L21/66

CPC分类号： G01R31/2884 ,  G01R31/307 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.

摘要翻译： 用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。 第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每一个中的第二线 对最初与第一金属互连级别下方的导电结构电隔离。 第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。