公开(公告)号：US08009215B2

公开(公告)日：2011-08-30

申请号：US12174264

申请日：2008-07-16

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/37452

Abstract: A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

Abstract translation: 在CMOS图像传感器的保持栅晶体管和传输栅极晶体管之间提供一组帧传输晶体管，以便能够在曝光之后存储在感光二极管中产生的电荷。 可以在CMOS图像传感器的多次曝光之后，在每个帧转移晶体管中的每个电荷向着传输门晶体管移动之前执行来自该组帧转移晶体管的电荷的读出。 启用有用的操作模式，包括用于快速捕获连续图像的突发模式操作和其中以不同曝光时间拍摄多个图像的高动态范围操作，或者通过组合帧传输晶体管的扩散来提供大的电容。

公开(公告)号：US20090242949A1

公开(公告)日：2009-10-01

申请号：US12056305

申请日：2008-03-27

Applicant: James W. Adkisson ,  Rajendran Krishnasamy

Inventor： James W. Adkisson ,  Rajendran Krishnasamy

IPC: H01L31/113 ,  H01L31/18

CPC classification number: H01L27/14603

Abstract: A carbon-containing semiconductor layer is formed on exposed surfaces of a p-doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.

Abstract translation: 在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。 在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。 随后形成浅沟槽隔离结构和光电二极管。 现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。 此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

公开(公告)号：US08298853B2

公开(公告)日：2012-10-30

申请号：US12853795

申请日：2010-08-10

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

IPC: H01L21/00

CPC classification number: H01L31/1136 ,  H01L27/14614 ,  H01L27/14643 ,  H01L27/14689

Abstract: CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates.

Abstract translation: 本文提供具有间隔物传输门的CMOS像素传感器单元和制造方法。 该方法包括在栅极电介质上形成中间栅极结构。 该方法还包括在中间栅极结构上形成绝缘侧壁。 该方法还包括在中间栅极的相对侧上的栅极电介质上形成间隔物传输门，邻近绝缘侧壁，隔离侧壁将中间栅极结构与间隔物传输门隔离。 该方法还包括形成光电二极管区域与间隔物传递门中的一个电气接触，以及浮动扩散部分与另一个间隔物传送门电接触。

公开(公告)号：US20110008925A1

公开(公告)日：2011-01-13

申请号：US12885648

申请日：2010-09-20

Applicant: James W. Adkisson ,  Rajendran Krishnasamy

Inventor： James W. Adkisson ,  Rajendran Krishnasamy

IPC: H01L31/18

CPC classification number: H01L27/14603

Abstract: A carbon-containing semiconductor layer is formed on exposed surfaces of a p− doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.

Abstract translation: 在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。 在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。 随后形成浅沟槽隔离结构和光电二极管。 现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。 此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

公开(公告)号：US08105861B2

公开(公告)日：2012-01-31

申请号：US12885648

申请日：2010-09-20

Applicant: James W. Adkisson ,  Rajendran Krishnasamy

Inventor： James W. Adkisson ,  Rajendran Krishnasamy

IPC: H01L21/00

CPC classification number: H01L27/14603

Abstract: A carbon-containing semiconductor layer is formed on exposed surfaces of a p− doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.

Abstract translation: 在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。 在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。 随后形成浅沟槽隔离结构和光电二极管。 现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。 此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

公开(公告)号：US08009216B2

公开(公告)日：2011-08-30

申请号：US12174289

申请日：2008-07-16

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/37452 ,  H04N5/2355

Abstract: A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

公开(公告)号：US20090250733A1

公开(公告)日：2009-10-08

申请号：US12099339

申请日：2008-04-08

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

IPC: H01L31/00 ,  H01L21/00 ,  G06F9/45

CPC classification number: H01L27/14603

Abstract: A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region.

Abstract translation: 在CMOS图像传感器的栅电极上方形成拉伸应力产生结构，以在也是转移晶体管的源极区域的光电二极管的电荷收集阱和浮动漏极之间施加正常的拉伸应力 连接源极区域和浮动漏极的方向。 拉伸应力降低了源区域和转移晶体管的主体之间的势垒，以实现更快和更多地将源区域中的电荷转移到浮动漏极。 因此CMOS图像传感器中的图像滞后减少。 此外，由于施加到源极区域的正常拉伸应力，源极区域的充电容量也增强​​。

公开(公告)号：US07800147B2

公开(公告)日：2010-09-21

申请号：US12056305

申请日：2008-03-27

Applicant: James W. Adkisson ,  Rajendran Krishnasamy

Inventor： James W. Adkisson ,  Rajendran Krishnasamy

IPC: H01L31/068

CPC classification number: H01L27/14603

Abstract: A carbon-containing semiconductor layer is formed on exposed surfaces of a p− doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.

Abstract translation: 在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。 在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。 随后形成浅沟槽隔离结构和光电二极管。 现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。 此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

公开(公告)号：US20100013973A1

公开(公告)日：2010-01-21

申请号：US12174289

申请日：2008-07-16

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

IPC: H04N5/335

CPC classification number: H04N5/37452 ,  H04N5/2355

Abstract: A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

Abstract translation: 在CMOS图像传感器的保持栅晶体管和传输栅极晶体管之间提供一组帧传输晶体管，以便能够在曝光之后存储在感光二极管中产生的电荷。 可以在CMOS图像传感器的多次曝光之后，在每个帧转移晶体管中的每个电荷向着传输门晶体管移动之前执行来自该组帧转移晶体管的电荷的读出。 启用有用的操作模式，包括用于快速捕获连续图像的突发模式操作和其中以不同曝光时间拍摄多个图像的高动态范围操作，或者通过组合帧传输晶体管的扩散来提供大的电容。

公开(公告)号：US20100013972A1

公开(公告)日：2010-01-21

申请号：US12174264

申请日：2008-07-16

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

IPC: H04N5/335

CPC classification number: H04N5/37452

Abstract: A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.