公开(公告)号：US06475916B1

公开(公告)日：2002-11-05

申请号：US09483936

申请日：2000-01-18

申请人： James Yong Meng Lee ,  Yun Qiang Zhang ,  Chock Hing Gan ,  Ravi Sundaresan

发明人： James Yong Meng Lee ,  Yun Qiang Zhang ,  Chock Hing Gan ,  Ravi Sundaresan

IPC分类号： H01L21302

CPC分类号： H01L21/28238 ,  H01L21/28211 ,  H01L21/3185 ,  H01L29/66553 ,  H01L29/66583

摘要： A new method is provided for the creation of ultra-thin gate oxide layers. Under the first embodiment, sacrificial oxide and nitride are deposited, openings are created in the layer of nitride where the ultra-thin layer of gate oxide is to be created. A layer of poly is deposited over the layer of nitride. The layer of polysilicon is polished, leaving the poly deposited inside the openings. The nitride is removed leaving the gate structure in place overlying the grown gate oxide. Under the second embodiment, sacrificial oxide and nitride are deposited followed by the deposition of TEOS oxide. The layers of TEOS, oxide and nitride are patterned creating openings that expose the surface areas of the layer of sacrificial oxide where the ultra-thin layers of gate oxide are to be grown. A thin conformal layer of nitride is deposited over the structure, this thin layer of conformal nitride is etched to form thin spacers on the sidewalls of the openings in the layers of TEOS oxide and nitride. Pre-gate clean is performed that removes the TEOS oxide and the sacrificial oxide on the bottom of the openings, gate oxidation is performed creating the ultra-thin layers of gate oxide. Poly is deposited, polished back followed by removal of the nitride leaving the poly gate structure in place and overlying the ultra-thin layer of gate oxide.

摘要翻译： 提供了一种新的制造超薄栅氧化层的方法。 在第一实施例中，沉积牺牲氧化物和氮化物，在氮化物层中产生开口，其中将形成栅极氧化物的超薄层。 一层多晶硅沉积在氮化物层上。 抛光多晶硅层，留下多孔沉积在开口内。 去除氮化物，留下栅极结构覆盖生长的栅极氧化物的位置。 在第二实施例中，沉积牺牲氧化物和氮化物，然后沉积TEOS氧化物。 TEOS，氧化物和氮化物的层被图案化以产生露出氧化物层的表面区域的开口，其中栅极氧化物的超薄层将被生长。 在结构上沉积薄的氮化层保形层，蚀刻该薄层的共形氮化物以在TEOS氧化物和氮化物层中的开口的侧壁上形成薄的间隔物。 进行预栅极清洁，其去除了开口底部的TEOS氧化物和牺牲氧化物，进行栅极氧化，产生栅极氧化物的超薄层。 将Poly沉积，抛光，然后除去留下多晶硅栅结构的氮化物，并覆盖栅极氧化物的超薄层。

公开(公告)号：US06309933B1

公开(公告)日：2001-10-30

申请号：US09584427

申请日：2000-06-05

申请人： Xia Li ,  Chock Hing Gan

发明人： Xia Li ,  Chock Hing Gan

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66537

摘要： A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate. The etched upper SiN, upper oxide, and lower SiN layers are removed to expose the T-shaped gate extending above the pad dielectric layer. An uppermost oxide layer is formed over the exposed T-shaped gate. SiN sidewall spacers are formed adjacent the exposed vertical side walls of the lower polysilicon gate portion. Silicide regions are formed over the T-shaped gate and source/drain regions.

摘要翻译： 一种制造半导体晶体管器件的方法，包括以下步骤。 提供了半导体结构，其具有上硅层，上硅层上的焊盘电介质层以及在上硅层中的阱区内的阱注入。 沉积下SiN层并在焊盘介电层上图案化以限定下栅极区域。 蚀刻下部栅极区内的焊盘电介质层和上部硅层形成具有预定宽度的下部栅极沟槽。 在下栅极沟槽内形成下栅极部分。 在下部SiN层上形成上部氧化物层。 在上氧化物层上方形成上层SiN层。 蚀刻上部SiN层以限定具有大于下部栅极沟槽预定宽度的预定宽度的上部栅极沟槽。 上栅极部分形成在上栅极沟槽内，其中下栅极部分和上栅极部分形成T形栅极。 去除蚀刻的上部SiN，上部氧化物层和下部SiN层，露出在焊盘介质层上方延伸的T形栅极。 在暴露的T形门上方形成最上层的氧化层。 在下多晶硅栅极部分的暴露的垂直侧壁附近形成SiN侧壁间隔物。 硅化物区域形成在T形栅极和源极/漏极区域上。

公开(公告)号：US06303458B1

公开(公告)日：2001-10-16

申请号：US09166732

申请日：1998-10-05

申请人： Yunqiang Zhang ,  Gang Qian ,  Chock Hing Gan

发明人： Yunqiang Zhang ,  Gang Qian ,  Chock Hing Gan

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabrication an alignment mark in a semiconductor device. The method uses one mask to that has two functions (1) a reverse active areas mask to remove the oxide from over active areas in the device areas and (2) an alignment mark open mask that removes the oxide from over the alignment mark area. The mask improves chemical-mechanical polish performance in the cell areas by removing the oxide over the active areas. Another key feature of the invention is the spacing of the alignment mark trenches that ensures that the step distance between the top of the second insulating layer in the alignment mark trench and the top surface of the substrate is greater than 2000 Å. This insures that the alignment marks are readable.

摘要翻译： 一种在半导体器件中制造对准标记的方法。 该方法使用一个掩模具有两个功能（1）反向有源区掩模，以从器件区域中的过度有效区域去除氧化物;以及（2）对准标记开口掩模，其从对准标记区域上方去除氧化物。 该掩模通过去除活性区域上的氧化物来改善细胞区域中的化学 - 机械抛光性能。 本发明的另一个关键特征是对准标记沟槽的间隔，其确保对准标记沟槽中的第二绝缘层的顶部与衬底的顶表面之间的台阶距离大于2000。 这确保对准标记是可读的。

公开(公告)号：US06531380B2

公开(公告)日：2003-03-11

申请号：US09968831

申请日：2001-10-03

申请人： Xia Li ,  Chock Hing Gan

发明人： Xia Li ,  Chock Hing Gan

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66537

摘要： A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate. The etched upper SiN, upper oxide, and lower SiN layers are removed to expose the T-shaped gate extending above the pad dielectric layer. An uppermost oxide layer is formed over the exposed T-shaped gate. SiN sidewall spacers are formed adjacent the exposed vertical side walls of the lower polysilicon gate portion. Silicide regions are formed over the T-shaped gate and source/drain regions.

公开(公告)号：US6165869A

公开(公告)日：2000-12-26

申请号：US96047

申请日：1998-06-11

申请人： Gang Qian ,  Chock Hing Gan ,  Lap Hung Chan ,  Poh Suan Tan

发明人： Gang Qian ,  Chock Hing Gan ,  Lap Hung Chan ,  Poh Suan Tan

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method is described for filling trenches with dielectric for shallow trench isolation which completely fills the trench and avoids problems due to dishing at the top of the trench. A trench is formed in a substrate having a second dielectric material formed thereon. The trench is lined with a third dielectric material. Sub atmospheric chemical vapor deposition, SACVD, of tetra-ethyl-ortho-silicate and ozone is used to grow a fourth dielectric on the surface of the second dielectric material and in the trench lined with the third dielectric material. The growth rate of fourth dielectric on the third dielectric is greater than the growth rate of the fourth dielectric on the second dielectric using SACVD of tetra-ethyl-ortho-silicate and ozone. The difference in growth rate assures that the trench is completely filled with fourth dielectric even for relatively thin layers of fourth dielectric grown on the second dielectric. This provides good planarity for a planarized substrate and avoids the problem of dishing at the top of the trench.

摘要翻译： 描述了一种用于填充具有用于浅沟槽隔离的电介质的沟槽的方法，其完全填充沟槽并且避免了由于沟槽顶部的凹陷引起的问题。 在其上形成有第二电介质材料的基板中形成沟槽。 沟槽衬有第三介电材料。 使用四乙基原硅酸盐和臭氧的次大气化学气相沉积，SACVD在第二介电材料的表面上和在第三介电材料内衬的沟槽中生长第四电介质。 第四电介质的第四电介质的生长速率大于使用四乙基原硅酸盐和臭氧的SACVD的第二电介质上的第四电介质的生长速率。 生长速率的差异确保即使对于在第二电介质上生长的第四电介质的较薄层，沟槽也完全填充第四电介质。 这为平坦化衬底提供了良好的平面性，并且避免了在沟槽顶部的凹陷的问题。