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    System and method for providing voltage supply protection in a memory device
    3.
    发明授权
    System and method for providing voltage supply protection in a memory device 有权
    在存储器件中提供电压保护的系统和方法

    公开(公告)号：US09251864B2

    公开(公告)日：2016-02-02

    申请号：US13605129

    申请日：2012-09-06

    申请人： Jan Otterstedt ,  Wolf Allers ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro ,  Thomas Kern

    发明人： Jan Otterstedt ,  Wolf Allers ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro ,  Thomas Kern

    IPC分类号： G11C29/04 ,  G11C29/02 ,  G11C5/14

    CPC分类号： G11C29/83 ,  G11C5/143 ,  G11C29/02 ,  G11C29/04 ,  G11C29/832

    摘要： The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.

    摘要翻译： 本发明涉及一种电子存储器系统，更具体地说，涉及一种用于在存储器件中提供电压保护的系统，以及一种在存储器件中提供电压保护的方法。 根据实施例，提供了一种用于在存储器件中提供电压保护的系统，该系统包括一个存储器阵列，该存储器阵列包括布置在多组存储器单元中的多个存储单元，以及多个限流元件，其中 每组存储器单元与至少一个限流元件相关联。

    System and Method for Providing Voltage Supply Protection in a Memory Device
    4.
    发明申请
    System and Method for Providing Voltage Supply Protection in a Memory Device 有权
    在存储器件中提供电压保护的系统和方法

    公开(公告)号：US20140064011A1

    公开(公告)日：2014-03-06

    申请号：US13605129

    申请日：2012-09-06

    申请人： Jan Otterstedt ,  Wolf Allers ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro ,  Thomas Kern

    发明人： Jan Otterstedt ,  Wolf Allers ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro ,  Thomas Kern

    IPC分类号： G11C5/14

    CPC分类号： G11C29/83 ,  G11C5/143 ,  G11C29/02 ,  G11C29/04 ,  G11C29/832

    摘要： The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.

    摘要翻译： 本发明涉及一种电子存储器系统，更具体地说，涉及一种用于在存储器件中提供电压保护的系统，以及一种在存储器件中提供电压保护的方法。 根据实施例，提供了一种用于在存储器件中提供电压保护的系统，该系统包括一个存储器阵列，该存储器阵列包括布置在多组存储器单元中的多个存储单元，以及多个限流元件，其中 每组存储器单元与至少一个限流元件相关联。

    Mismatch error reduction method and system for STT MRAM
    5.
    发明授权
    Mismatch error reduction method and system for STT MRAM 有权
    STT MRAM的不匹配误差减少方法和系统

    公开(公告)号：US09070466B2

    公开(公告)日：2015-06-30

    申请号：US13605693

    申请日：2012-09-06

    申请人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    发明人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1673

    摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.

    摘要翻译： 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 根据本发明的一个方面，一种用于读取存储单元的方法包括将来自存储单元的单元电流与来自参考源的参考电流组合以产生平均电流，使平均电流能够流过第一镜像晶体管 在参考路径中的感测路径和第二镜像晶体管中，将电流失配存储在耦合到第一镜面晶体管和第二镜像晶体管的栅极的电容器上，将存储器单元与参考路径断开并将参考源与 感测路径，使得电池电流仅能够流过感测路径，并且确定存储器单元的输出电平。

    Differential sensing method and system for STT MRAM
    6.
    发明授权
    Differential sensing method and system for STT MRAM 有权
    STT MRAM差分感测方法及系统

    公开(公告)号：US08837210B2

    公开(公告)日：2014-09-16

    申请号：US13592404

    申请日：2012-08-23

    申请人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    发明人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    IPC分类号： G11C11/00

    CPC分类号： G11C29/028 ,  G11C11/16 ,  G11C11/1673 ,  G11C29/021 ,  G11C2029/5006

    摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.

    摘要翻译： 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 根据本发明的一个方面，用于读取存储单元的系统包括读取通道和预充电路径。 参考电流通过读取路径提供，并通过读取路径中的采样元件进行采样。 随后，通过相同的采样元件和读取路径提供来自存储单元的电流。 然后，输出电平由针对采样参考电流工作的电池电流确定。

    Memory cell, a method for forming a memory cell, and a method for operating a memory cell
    7.
    发明授权
    Memory cell, a method for forming a memory cell, and a method for operating a memory cell 有权
    存储单元，用于形成存储单元的方法，以及用于操作存储单元的方法

    公开(公告)号：US08649205B2

    公开(公告)日：2014-02-11

    申请号：US13370377

    申请日：2012-02-10

    申请人： Christian Peters ,  Mihail Jefremow ,  Jan Otterstedt ,  Wolf Allers ,  Robert Wiesner

    发明人： Christian Peters ,  Mihail Jefremow ,  Jan Otterstedt ,  Wolf Allers ,  Robert Wiesner

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673 ,  G11C11/16 ,  G11C2213/78

    摘要： A memory cell is provided, the memory cell including a first two-terminal memory element; a second two-terminal memory element; a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.

    摘要翻译： 提供存储单元，所述存储单元包括第一两端存储单元; 第二个两端存储元件; 控制器电路，被配置为将所述第一两端存储元件编程为一个或多个状态，将所述第二二端存储元件编程为一个或多个状态，其中，所述第一二端存储元件的状态和所述第二二端存储元件的状态 终端记忆元素是相互依存的; 以及测量电路，被配置为测量与第一两端存储元件的状态相关联的第一两端存储元件信号与第二二端存储元件的状态相关的第二二端存储元件信号之间的差分信号 记忆元素

    MEMORY CELL, A METHOD FOR FORMING A MEMORY CELL, AND A METHOD FOR OPERATING A MEMORY CELL
    8.
    发明申请
    MEMORY CELL, A METHOD FOR FORMING A MEMORY CELL, AND A METHOD FOR OPERATING A MEMORY CELL 有权
    存储单元，形成存储单元的方法，以及操作存储单元的方法

    公开(公告)号：US20130208527A1

    公开(公告)日：2013-08-15

    申请号：US13370377

    申请日：2012-02-10

    申请人： Christian Peters ,  Mihail Jefremow ,  Jan Otterstedt ,  Wolf Allers ,  Robert Wiesner

    发明人： Christian Peters ,  Mihail Jefremow ,  Jan Otterstedt ,  Wolf Allers ,  Robert Wiesner

    IPC分类号： G11C11/00 ,  G11C5/00 ,  G11C11/16

    CPC分类号： G11C11/1673 ,  G11C11/16 ,  G11C2213/78

    摘要： A memory cell is provided, the memory cell including a first two-terminal memory element; a second two-terminal memory element; a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.

    摘要翻译： 提供存储单元，所述存储单元包括第一两端存储单元; 第二个两端存储元件; 控制器电路，被配置为将所述第一两端存储元件编程为一个或多个状态，将所述第二二端存储元件编程为一个或多个状态，其中，所述第一二端存储元件的状态和所述第二二端存储元件的状态 终端记忆元素是相互依存的; 以及测量电路，被配置为测量与第一两端存储元件的状态相关联的第一两端存储元件信号与第二二端存储元件的状态相关的第二二端存储元件信号之间的差分信号 记忆元素

    Mismatch Error Reduction Method and System for STT MRAM
    9.
    发明申请
    Mismatch Error Reduction Method and System for STT MRAM 有权
    STT MRAM的不匹配误差减少方法和系统

    公开(公告)号：US20140063923A1

    公开(公告)日：2014-03-06

    申请号：US13605693

    申请日：2012-09-06

    申请人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    发明人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    IPC分类号： G11C7/06 ,  G11C11/16

    CPC分类号： G11C11/1673

    摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.

    摘要翻译： 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 根据本发明的一个方面，一种用于读取存储单元的方法包括将来自存储单元的单元电流与来自参考源的参考电流组合以产生平均电流，使平均电流能够流过第一镜像晶体管 在参考路径中的感测路径和第二镜像晶体管中，将电流失配存储在耦合到第一镜面晶体管和第二镜像晶体管的栅极的电容器上，将存储器单元与参考路径断开并将参考源与 感测路径，使得电池电流仅能够流过感测路径，并且确定存储器单元的输出电平。

    Differential Sensing Method and System for STT MRAM
    10.
    发明申请
    Differential Sensing Method and System for STT MRAM 有权
    STT MRAM差分传感方法及系统

    公开(公告)号：US20140056058A1

    公开(公告)日：2014-02-27

    申请号：US13592404

    申请日：2012-08-23

    申请人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    发明人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    IPC分类号： G11C7/12 ,  G11C11/16 ,  G11C7/00

    CPC分类号： G11C29/028 ,  G11C11/16 ,  G11C11/1673 ,  G11C29/021 ,  G11C2029/5006

    摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.

    摘要翻译： 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 根据本发明的一个方面，用于读取存储单元的系统包括读取通道和预充电路径。 参考电流通过读取路径提供，并通过读取路径中的采样元件进行采样。 随后，通过相同的采样元件和读取路径提供来自存储单元的电流。 然后，输出电平由针对采样参考电流工作的电池电流确定。