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公开(公告)号：US07174486B2
公开(公告)日：2007-02-06
申请号：US10303444
申请日：2002-11-22
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , H03K19/1735
摘要： A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.
摘要翻译： 一种用于修复半导体芯片中的缺陷存储器的方法和系统。 该芯片具有存储器位置，冗余存储器和用于有序保险丝的中心位置。 有序保险丝以压缩格式识别存储器位置的缺陷部分。 有缺陷的部分可由冗余存储器的部分替换。 有序保险丝具有相关联的熔丝位模式，其顺序地表示压缩格式的缺陷部分。 方法和系统确定存储器位置连接在一起的顺序; 根据存储器位置连接在一起的顺序，通过存储器位置设计锁存器的移位寄存器; 并且将每个锁存器与从其导出熔丝位模式的未压缩位模式的对应位相关联。 未压缩比特模式包括一个比特序列，表示未压缩格式的缺陷部分。
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公开(公告)号：US08024626B2
公开(公告)日：2011-09-20
申请号：US11552166
申请日：2006-10-24
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , H03K19/1735
摘要： A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.
摘要翻译： 一种用于修复半导体芯片中的有缺陷的存储器的方法和系统。 该芯片具有存储器位置，冗余存储器和用于有序保险丝的中心位置。 有序保险丝以压缩格式识别存储器位置的缺陷部分。 有缺陷的部分可由冗余存储器的部分替换。 有序保险丝具有相关联的熔丝位模式，其顺序地表示压缩格式的缺陷部分。 方法和系统确定存储器位置连接在一起的顺序; 根据存储器位置连接在一起的顺序，通过存储器位置设计锁存器的移位寄存器; 并且将每个锁存器与从其导出熔丝位模式的未压缩位模式的对应位相关联。 未压缩比特模式包括一个比特序列，表示未压缩格式的缺陷部分。
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公开(公告)号：US06505324B1
公开(公告)日：2003-01-07
申请号：US09680340
申请日：2000-10-05
申请人： Bruce Cowan , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner , Dora R. Pealer , Bruce D. Raymond , Paul S. Zuchowski
发明人： Bruce Cowan , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner , Dora R. Pealer , Bruce D. Raymond , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G11C29/72 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/56 , G11C2029/5604 , G11C2029/5606
摘要： It is, therefore, an object of the present invention to provide a structure and method of blowing fuses in a semiconductor chip that includes creating a design for the chip using a library, generating test data from the design, extracting the fuse related information from the design to prepare a fuse blow table, building the chip with the design data, testing the chip to produce failed data, comparing the fuse blow table to the failed data to determine the fuse blow location data, and blowing the selected fuses based on the fuse blow location data. The extraction method can include creating a fuse map file based upon a correlation between physical pin locations on the chip and different fuse macros within the design, wherein an order of fuses within the fuse blow table matches an order of fuses within the fuse map file.
摘要翻译： 因此，本发明的目的是提供一种在半导体芯片中熔断熔丝的结构和方法，该结构和方法包括使用库创建芯片的设计，从设计中产生测试数据，从熔丝相关信息中提取熔丝相关信息 设计准备保险丝打火台，用设计数据构建芯片，测试芯片产生故障数据，比较保险丝熔断台与故障数据，确定保险丝熔断位置数据，并根据保险丝吹送选定的保险丝 吹打位置数据。 提取方法可以包括基于芯片上的物理引脚位置与设计中的不同熔丝宏之间的相关性来创建熔丝图文件，其中保险丝熔断台内的保险丝顺序与熔丝映射文件内的熔丝顺序匹配。
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4.发明授权Security-enhanced radio frequency object locator system, method and program storage device 有权安全增强射频对象定位系统，方法和程序存储设备公开(公告)号：US08823491B2
公开(公告)日：2014-09-02
申请号：US13348866
申请日：2012-01-12
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译： 公开了一种对象定位器系统，方法和程序存储装置。 在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。 当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象的所需许可证，并且可选地，特定用户的身份被认证。 一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。 使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。 一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。
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公开(公告)号：US20140040685A1
公开(公告)日：2014-02-06
申请号：US13567127
申请日：2012-08-06
IPC分类号： G11C29/12
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译： 本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。 在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。
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6.发明申请SECURITY-ENHANCED RADIO FREQUENCY OBJECT LOCATOR SYSTEM, METHOD AND PROGRAM STORAGE DEVICE 有权安全增强无线电频率对象定位系统，方法和程序存储设备公开(公告)号：US20130181838A1
公开(公告)日：2013-07-18
申请号：US13348866
申请日：2012-01-12
IPC分类号： G08B13/14
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译： 公开了一种对象定位器系统，方法和程序存储装置。 在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。 当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象所需的许可，并且可选地，特定用户的身份被认证。 一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。 使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。 一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。
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7.发明授权Structure and method for storing multiple repair pass data into a fusebay 有权用于将多个修复传递数据存储到保险丝盒中的结构和方法公开(公告)号：US08467260B2
公开(公告)日：2013-06-18
申请号：US13198894
申请日：2011-08-05
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译： 相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。 每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。 连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。 在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。
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8.发明授权公开(公告)号：US07916826B2
公开(公告)日：2011-03-29
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。
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9.发明授权Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block 有权包含用于将状态恢复到功率管理功能块的多状态恢复电路的集成电路公开(公告)号：US07821294B2
公开(公告)日：2010-10-26
申请号：US12135249
申请日：2008-06-09
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , H03K19/173
摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.
摘要翻译： 多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。 多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。 多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。
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公开(公告)号：US07725780B2
公开(公告)日：2010-05-25
申请号：US11875011
申请日：2007-10-19
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.
摘要翻译： 用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。 存储器阵列（14）包括通用存储元件（18）和冗余存储元件（20）。 一般存储器元件（18）被测试，并且任何有缺陷的通用存储器元件（18）被替换为冗余存储元件（20）。 冗余存储器元件（20）仅在使能时被测试。
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