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公开(公告)号：US20140146035A1
公开(公告)日：2014-05-29
申请号：US14170854
申请日：2014-02-03
Inventor： Toshio MIYAZAWA , Iwao TAKEMOTO , Atsushi HASEGAWA , Masahiro MAKI , Kazutaka GOTO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A driving circuit for driving a display panel includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.
Abstract translation: 用于驱动显示面板的驱动电路包括以稳定的方式操作并且可以扩大设计自由度的动态无竞争移位寄存器。 在具有在衬底表面上由p-Si制成的半导体层的薄膜晶体管的动态无量纲移位寄存器中，通过电容元件将成为浮置状态的节点连接到固定电位。
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公开(公告)号：US20170270884A1
公开(公告)日：2017-09-21
申请号：US15611995
申请日：2017-06-02
Inventor： Toshio MIYAZAWA , Iwao TAKEMOTO , Atsushi HASEGAWA , Masahiro MAKI , Kazutaka GOTO
IPC: G09G3/36 , G11C19/28 , H01L29/423 , G11C19/18 , H01L27/12
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
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公开(公告)号：US20170053614A1
公开(公告)日：2017-02-23
申请号：US15290009
申请日：2016-10-11
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hiroaki KOMATSU
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2018 , G09G3/3674 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.
Abstract translation: 显示装置的驱动电路包括连续布置的第一至第三输出信号线，具有连接到第二输出信号线的源极和连接到第一时钟信号线的漏极的第一晶体管和提供 当第二时钟信号变为有效电位时，对第一晶体管的栅极的非有效电位，其中向第一输出信号线和第三输出信号线输出有效电位的电路设置在与第 电路，其具有介于其间的显示区域向第二输出信号线输出有效电位，并且其中第一晶体管的栅极经由整流电路连接到第一输出信号线和第三输出信号线。
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公开(公告)号：US20190122629A1
公开(公告)日：2019-04-25
申请号：US16225094
申请日：2018-12-19
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
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公开(公告)号：US20180374444A1
公开(公告)日：2018-12-27
申请号：US16106835
申请日：2018-08-21
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gats signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
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Patent Agency Ranking
公开(公告)号：US20170076686A1
公开(公告)日：2017-03-16
申请号：US15361785
申请日：2016-11-28
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: a gate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
Abstract translation: 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：栅极线高电压施加电路，其根据高信号周期导通，以将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。
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公开(公告)号：US20150346844A1
公开(公告)日：2015-12-03
申请号：US14825042
申请日：2015-08-12
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hiroaki KOMATSU
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2018 , G09G3/3674 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.
Abstract translation: 显示装置的驱动电路包括连续布置的第一至第三输出信号线，具有连接到第二输出信号线的源极和连接到第一时钟信号线的漏极的第一晶体管和提供 当第二时钟信号变为有效电位时，对第一晶体管的栅极的非有效电位，其中向第一输出信号线和第三输出信号线输出有效电位的电路设置在与第 电路，其具有介于其间的显示区域向第二输出信号线输出有效电位，并且其中第一晶体管的栅极经由整流电路连接到第一输出信号线和第三输出信号线。
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公开(公告)号：US20180068631A1
公开(公告)日：2018-03-08
申请号：US15808142
申请日：2017-11-09
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hiroaki KOMATSU
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2018 , G09G3/3674 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.
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公开(公告)号：US20170053613A1
公开(公告)日：2017-02-23
申请号：US15255338
申请日：2016-09-02
Inventor： Toshio MIYAZAWA , Iwao TAKEMOTO , Atsushi HASEGAWA , Masahiro MAKI , Kazutaka GOTO
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
Abstract translation: 具有移位寄存器的显示驱动电路形成在显示面板上。 移位寄存器包括具有第一和第二晶体管的第一级和具有第三和第四晶体管的第二级。 第一晶体管的控制电极的电压由第一脉冲线的电压从低升高。 在导通状态下，第二晶体管连接第一晶体管的控制电极和恒压线。 第三晶体管的控制电极的电压由第二脉冲线的电压从低到高升高。 在导通状态下，第四晶体管连接第三晶体管的控制电极和恒压线。 第四晶体管由来自第一级的信号导通。
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公开(公告)号：US20160063931A1
公开(公告)日：2016-03-03
申请号：US14938039
申请日：2015-11-11
Applicant: Japan Display Inc.
Inventor： Takayuki SUZUKI , Hiroyuki ABE , Masahiro MAKI , Mitsura GOTO
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
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