公开(公告)号：US20120216159A1

公开(公告)日：2012-08-23

申请号：US13403799

申请日：2012-02-23

申请人： Jason R. Baumgartner ,  Paul Roessler ,  Ohad Shacham ,  Jiazhao Xu

发明人： Jason R. Baumgartner ,  Paul Roessler ,  Ohad Shacham ,  Jiazhao Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.

摘要翻译： 用于验证使用安全性转换的逻辑设计的技术包括为网表的活动属性分配活动门，并分配单个循环门以为活跃门提供循环信号。 当没有活动门被断言时，防止单回路门的断言。 对网表的第一状态进行采样，并且采样的第一状态为在单循环门的断言之后的活动门中的至少一个为第一行为环提供初始状态。 将第一行为循环的采样第一状态与第一行为循环的稍后状态进行比较，以确定是否重复采样的第一状态。 当重复采样的第一状态并且在第一行为循环的持续时间内相关联的一个活动门保持断言时，返回活动违反。

公开(公告)号：US20100218150A1

公开(公告)日：2010-08-26

申请号：US12393779

申请日：2009-02-26

申请人： Jason R. Baumgartner ,  Paul Roessler ,  Ohad Shacham ,  Jiazhao Xu

发明人： Jason R. Baumgartner ,  Paul Roessler ,  Ohad Shacham ,  Jiazhao Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A technique for verification of a logic design (embodied in a netlist) using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of the netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.

摘要翻译： 使用活动到安全转换来验证逻辑设计（体现在网表中）的技术包括为网表的活动属性分配活动门，并且分配单个循环门以为活动门提供循环信号。 当没有活动门被断言时，防止单回路门的断言。 对网表的第一状态进行采样，并且采样的第一状态为在单循环门的断言之后的活动门中的至少一个为第一行为环提供初始状态。 将第一行为循环的采样的第一状态与第一行为循环的稍后状态进行比较，以确定是否重复采样的第一状态。 当重复采样的第一状态并且在第一行为循环的持续时间内相关联的一个活动门保持断言时，返回活动违反。

公开(公告)号：US08352894B2

公开(公告)日：2013-01-08

申请号：US13403799

申请日：2012-02-23

申请人： Jason R. Baumgartner ,  Paul Joseph Roessler ,  Ohad Shacham ,  Jiazhao Xu

发明人： Jason R. Baumgartner ,  Paul Joseph Roessler ,  Ohad Shacham ,  Jiazhao Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.

摘要翻译： 用于验证使用安全性转换的逻辑设计的技术包括为网表的活动属性分配活动门，并分配单个循环门以为活跃门提供循环信号。 当没有活动门被断言时，防止单回路门的断言。 对网表的第一状态进行采样，并且采样的第一状态为在单循环门的断言之后的活动门中的至少一个为第一行为环提供初始状态。 将第一行为循环的采样的第一状态与第一行为循环的稍后状态进行比较，以确定是否重复采样的第一状态。 当重复采样的第一状态并且在第一行为循环的持续时间内相关联的一个活动门保持断言时，返回活动违反。

公开(公告)号：US07856609B2

公开(公告)日：2010-12-21

申请号：US12164781

申请日：2008-06-30

申请人： Jason R. Baumgartner ,  Hari Mony ,  Viresh Paruthi ,  Jiazhao Xu

发明人： Jason R. Baumgartner ,  Hari Mony ,  Viresh Paruthi ,  Jiazhao Xu

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/504

摘要： A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.

摘要翻译： 用于生成用于生成用于集成电路设计的验证的约束的约束的方法包括识别所述设计的网表（N）中的目标并且创建所述网表的过近似抽象（N'）。 通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状​​态（S'）。 然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。 对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。 创建过近似抽象可能包括用随机门替换顺序门。 识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。

公开(公告)号：US20080282207A1

公开(公告)日：2008-11-13

申请号：US11746836

申请日：2007-05-10

申请人： Jason R. Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Jiazhao Xu

发明人： Jason R. Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Jiazhao Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method, apparatus and computer-readable medium for conjunctive binary decision diagram building and variable quantification using case-splitting are presented. A BDD building program builds a BDD for at least one node in a netlist graph representation of a circuit design. One or more variables are selected for case-splitting. The variable is set to a constant logical value and then the other. A BDD is built for each case. The program determines whether the variable is scheduled to be quantified out. If so, the program combines the BDDs for each case according to whether the quantification is existential or universal. If the variable is not scheduled to be quantified, the program combines the BDDs for each case so that the variable is introduced back into the resulting BDD, which has a reduced number of peak live nodes.

摘要翻译： 提出了一种用于连接二进制决策图构建和使用案例分解的可变量化的方法，装置和计算机可读介质。 BDD构建程序为电路设计的网表图表中的至少一个节点构建BDD。 选择一个或多个变量进行案例分解。 该变量设置为一个常量逻辑值，然后另一个。 BDD是为每种情况而建的。 该程序确定变量是否被调度为量化。 如果是这样，该程序根据量化是存在性还是普遍性来组合每个案例的BDD。 如果该变量未被调度为量化，则该程序将每个情况的BDD组合起来，以便该变量被引回到具有减少的峰值活动节点数量的结果BDD中。

公开(公告)号：US08201118B2

公开(公告)日：2012-06-12

申请号：US12475494

申请日：2009-05-30

申请人： Jason R. Baumgartner ,  Paul J. Roessler ,  Mark A. Williams ,  Jiazhao Xu

发明人： Jason R. Baumgartner ,  Paul J. Roessler ,  Mark A. Williams ,  Jiazhao Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： Methods and systems are provided for dynamically generating a hint set for enhanced reachability analysis in a sequential circuitry design that is represented by a Binary Decision Diagram (BDD). After determining a ranking of the BDD variables, they are sorted in the order of the ranking. The ranking is used to select some of the variables for use in creating hints for more efficiently performing the reachability analysis in a creating an equivalent sequential circuitry design.

摘要翻译： 提供了方法和系统，用于在由二进制决策图（BDD）表示的顺序电路设计中动态生成用于增强可达性分析的提示集。 在确定BDD变量的排名之后，按照排名的顺序进行排序。 排名被用于选择一些用于创建提示的变量，以在创建等效的顺序电路设计中更有效地执行可达性分析。

公开(公告)号：US07739635B2

公开(公告)日：2010-06-15

申请号：US11746836

申请日：2007-05-10

申请人： Jason R. Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Jiazhao Xu

发明人： Jason R. Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Jiazhao Xu

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/504

摘要： A method, apparatus and computer-readable medium for conjunctive binary decision diagram building and variable quantification using case-splitting are presented. A BDD building program builds a BDD for at least one node in a netlist graph representation of a circuit design. One or more variables are selected for case-splitting. The variable is set to a constant logical value and then the other. A BDD is built for each case. The program determines whether the variable is scheduled to be quantified out. If so, the program combines the BDDs for each case according to whether the quantification is existential or universal. If the variable is not scheduled to be quantified, the program combines the BDDs for each case so that the variable is introduced back into the resulting BDD, which has a reduced number of peak live nodes.

摘要翻译： 提出了一种用于连接二进制决策图构建和使用案例分解的可变量化的方法，装置和计算机可读介质。 BDD构建程序为电路设计的网表图表中的至少一个节点构建BDD。 选择一个或多个变量进行案例分解。 该变量设置为一个常量逻辑值，然后另一个。 BDD是为每种情况而建的。 该程序确定变量是否被调度为量化。 如果是这样，该程序根据量化是存在性还是普遍性来组合每个案例的BDD。 如果该变量未被调度为量化，则该程序将每个情况的BDD组合起来，以便该变量被引回到具有减少的峰值活动节点数量的结果BDD中。

公开(公告)号：US07836413B2

公开(公告)日：2010-11-16

申请号：US11963325

申请日：2007-12-21

申请人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Oliver Weber

发明人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Oliver Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/30958 ,  G06F17/504 ,  Y10S707/99942

摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.

摘要翻译： 公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。 该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。 然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定 使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。 响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。 响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。

公开(公告)号：US20060047680A1

公开(公告)日：2006-03-02

申请号：US10926587

申请日：2004-08-26

申请人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Weber

发明人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Weber

IPC分类号： G06F7/00

CPC分类号： G06F17/30958 ,  G06F17/504 ,  Y10S707/99942

摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.

摘要翻译： 公开了一种用于使用动态资源约束和交错深度优先搜索和修改的宽度优先搜索时间表在数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。 该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。 然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定 使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。 响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。 响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。

公开(公告)号：US07853917B2

公开(公告)日：2010-12-14

申请号：US11963267

申请日：2007-12-21

申请人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Oliver Weber

发明人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Oliver Weber

IPC分类号： G06H17/50

CPC分类号： G06F17/30958 ,  G06F17/504 ,  Y10S707/99942

摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.

摘要翻译： 公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。 该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。 然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定 使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。 响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。 响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。