公开(公告)号：US5654746A

公开(公告)日：1997-08-05

申请号：US352162

申请日：1994-12-01

申请人： Jay C. McMullan, Jr. ,  David B. Burleson ,  Paul Borsetti, Jr. ,  John T. Filion

发明人： Jay C. McMullan, Jr. ,  David B. Burleson ,  Paul Borsetti, Jr. ,  John T. Filion

IPC分类号： G06F21/22 ,  A63F13/06 ,  A63F13/12 ,  G06F13/00 ,  G09C1/00 ,  H04N7/16 ,  H04N7/167 ,  H04N21/81 ,  H04N7/10 ,  H04H1/02 ,  H04H7/00

CPC分类号： A63F13/73 ,  A63F13/12 ,  A63F13/71 ,  A63F13/77 ,  H04N21/8166 ,  H04N7/165 ,  H04N7/1675 ,  A63F2300/206 ,  A63F2300/401 ,  A63F2300/409 ,  A63F2300/532 ,  A63F2300/552 ,  A63F2300/636

摘要： A communications system for the delivery of digital data programs to a remote location includes a transmitter for transmitting a signal having the digital data programs and a communications terminal located at the remote location. The communications terminal includes a control circuit including authorizing circuitry responsive to authorization data for authorizing the communications terminal to access authorized ones of the digital data programs in one of a first and a second authorization mode. For example, automatic authorization modes for game play may comprise an arcade mode and a rental mode, simulating manual access methods i.e. paying for play at a video arcade or for rental of games from a video game store. Moreover, new games may be accessed without charge by the game player if authorized according to a free service authorization map. Furthermore, parents may limits game play to children prior to a particular time of day such as bed-time or to a maximum playtime limit according to a secret downloadbale password known only to the parents. A game player may only read and not write authorization and control data.

公开(公告)号：US5557782A

公开(公告)日：1996-09-17

申请号：US273763

申请日：1994-07-12

申请人： Todd R. Witkowski ,  Vincent J. Messina ,  Richard D. Ball ,  John T. Filion

发明人： Todd R. Witkowski ,  Vincent J. Messina ,  Richard D. Ball ,  John T. Filion

IPC分类号： G06F13/42 ,  G06F12/00

CPC分类号： G06F13/4243

摘要： A computer system has a memory and has a processor coupled to the memory, the processor having an access control arrangement for delaying completion of a memory access until the occurrence of a control signal. A deterministic circuit coupled to the-processor and the memory has a register arrangement containing control information loaded by the processor, the deterministic circuit having a signal generation arrangement for generating the control signal. The signal generating arrangement includes a selective delay arrangement which can selectively delay generation of the control signal during an access to the memory by a time interval having a duration which is a function of the control information in the register arrangement.

摘要翻译： 计算机系统具有存储器并且具有耦合到存储器的处理器，该处理器具有用于延迟存储器访问的完成的访问控制装置，直到出现控制信号。 耦合到处理器和存储器的确定性电路具有包含由处理器加载的控制信息的寄存器布置，确定性电路具有用于产生控制信号的信号产生装置。 信号产生装置包括选择性延迟装置，其可以在存储器访问期间选择性地延迟控制信号的产生，该时间间隔具有作为寄存器装置中的控制信息的函数的持续时间。