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    Reliable global broadcasting in a multistage network
    1.
    发明申请
    Reliable global broadcasting in a multistage network 审中-公开
    在多级网络中可靠的全球广播

    公开(公告)号：US20070253426A1

    公开(公告)日：2007-11-01

    申请号：US11413526

    申请日：2006-04-28

    申请人： Jay Herring ,  Aruna Ramanan ,  Craig Stunkel

    发明人： Jay Herring ,  Aruna Ramanan ,  Craig Stunkel

    IPC分类号： H04L12/56

    CPC分类号： H04L12/18 ,  H04L49/1515 ,  H04L49/201 ,  H04L49/25 ,  H04L49/40 ,  H04L49/65

    摘要： Efficient, reliable broadcast support is provided to clients of a network built using switching elements that have the capability to replicate packets. Replication patterns are generated and used in broadcasting data in the network. The replication patterns are provided in hardware of the network to enable broadcasting from one node in the network to each node of a broadcast domain of the network.

    摘要翻译： 向使用能够复制数据包的交换单元构建的网络的客户端提供高效，可靠的广播支持。 复制模式被生成并用于广播网络中的数据。 在网络的硬件中提供复制模式，以使得能够从网络中的一个节点广播到网络的广播域的每个节点。

    Method and system for an on-chip AC self-test controller
    3.
    发明申请
    Method and system for an on-chip AC self-test controller 有权

    公开(公告)号：US20060242509A1

    公开(公告)日：2006-10-26

    申请号：US11323449

    申请日：2005-12-30

    申请人： John Flanagan ,  Jay Herring ,  Tin-Chee Lo

    发明人： John Flanagan ,  Jay Herring ,  Tin-Chee Lo

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31724 ,  G01R31/2891 ,  G01R31/31922

    摘要： An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at speed data launch pulse is applied to the first test register in response to said system clock. The data from the first register is input to a logic path in response to applying the at speed data launch pulse to the first test register. An at speed data capture pulse is applied to a second test register in response to the system clock. The output from the logic path is input to the second test register in response to applying the at speed data capture pulse to the second test register. A long data launch pulse is applied to the second test register in response to the system clock. An additional embodiment includes a system for performing AC self-test on an integrated circuit that includes a system clock.

    Method, system and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables
    5.
    发明申请
    Method, system and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables 失效
    方法，系统和程序产品，用于通过使用多种转发表的数据传输网络的节点促进数据分组的转发

    公开(公告)号：US20050149600A1

    公开(公告)日：2005-07-07

    申请号：US10737989

    申请日：2003-12-17

    申请人： Jay Herring ,  Scot Rider

    发明人： Jay Herring ,  Scot Rider

    IPC分类号： H04L12/56 ,  G06F15/16

    CPC分类号： H04L45/742 ,  H04L45/00 ,  H04L45/54

    摘要： Method, system and program product are provided for reducing size of memory required for a switching node's forwarding table by employing forwarding tables of different types to map received data packets addressed to downstream nodes and upstream nodes to appropriate output ports of the switching node. The method includes receiving a data packet at a data transfer node of a network and selecting a forwarding table from multiple types of forwarding tables accessible by the node based on an attribute associated with the received data packet, and mapping the data packet to an output port of the node utilizing the forwarding table selected from the multiple types of forwarding tables based on the attribute associated with the packet.

    摘要翻译： 提供方法，系统和程序产品，用于通过采用不同类型的转发表来将接收到的下游节点和上游节点的数据分组映射到交换节点的适当输出端口来减少交换节点的转发表所需的存储器的大小。 该方法包括在网络的数据传输节点处接收数据分组，并且基于与接收到的数据分组相关联的属性，从节点可访问的多种类型的转发表中选择转发表，并将数据分组映射到输出端口 基于与分组关联的属性，利用从多种类型的转发表中选择的转发表来使用该节点。

    Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit
    6.
    发明申请
    Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit 失效
    用于控制集成电路逻辑内置自检的测试数据的方法，系统和程序产品

    公开(公告)号：US20060107149A1

    公开(公告)日：2006-05-18

    申请号：US10980938

    申请日：2004-11-04

    申请人： Marvin Rich ,  Jay Herring

    发明人： Marvin Rich ,  Jay Herring

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318547

    摘要： A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.

    摘要翻译： 提供了一种利用具有多个锁存器的边界锁存模块来控制测试数据的方法，以便于集成电路（IC）的内部自检的逻辑，其包括提供多个选择装置，用于选择初始化数据以存储在 IC边界锁存模块的多个锁存器。 初始化数据从集成电路的多个扫描路径中选择，并且来自至少一个锁存器的初始化数据被提供作为IC的逻辑电路或IC的输出的输入。 在另一方面，该方法包括从集成电路的外部输入或测试模式发生器中选择一个数据，用于在至少一个锁存器中捕获并输入到多输入签名寄存器，多个输入签名寄存器存储集成电路的签名 由逻辑内置的自检产生。

    Method, system and program product for actively managing central queue buffer allocation
    7.
    发明申请
    Method, system and program product for actively managing central queue buffer allocation 失效
    方法，系统和程序产品，用于主动管理中央队列缓冲区分配

    公开(公告)号：US20050226145A1

    公开(公告)日：2005-10-13

    申请号：US10822794

    申请日：2004-04-09

    申请人： Derrick Garmire ,  Jay Herring ,  Ronald Linton ,  Scot Rider

    发明人： Derrick Garmire ,  Jay Herring ,  Ronald Linton ,  Scot Rider

    IPC分类号： H04L12/28 ,  H04L12/56

    CPC分类号： H04L49/9063 ,  H04L49/3036 ,  H04L49/3045 ,  H04L49/90 ,  H04L49/9057 ,  H04L49/9078

    摘要： Method, system and program product are provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

    摘要翻译： 提供方法，系统和程序产品用于数据传输网络的交换节点的分组流控制。 该方法包括基于当前在中央队列中可用的未使用空间的量，主动地管理分配给交换节点的端口的交换节点的中心队列中的空间分配。 在另一方面，该方法包括分别跟踪未分配的空间和空闲的分配空间，其已被用于缓冲由端口接收的分组，但是由于从中央队列中移除分组而进行的先前的管理更新。 每个端口都提供空闲空间，目前分配给该端口和中央队列中当前未分配空间的数量，以分配到端口的一个或多个虚拟通道。

    Simultaneous AC logic self-test of multiple clock domains
    8.
    发明申请
    Simultaneous AC logic self-test of multiple clock domains 有权
    多个时钟域的同步交流逻辑自检

    公开(公告)号：US20050166104A1

    公开(公告)日：2005-07-28

    申请号：US10753801

    申请日：2004-01-08

    申请人： Marvin Rich ,  Jay Herring ,  Ronald Linton

    发明人： Marvin Rich ,  Jay Herring ,  Ronald Linton

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20

    CPC分类号： G01R31/318577 ,  G01R31/31725

    摘要： A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock domains. A clock command is generated by an on product clock generator for each clock domain simultaneously; and an asynchronous receive clock driver provides a programmable delay to a capture clock based on predetermined cycle requirements of the asynchronous boundaries. Asynchronous boundary test requirements are defined exclusively from the perspective of the asynchronous boundary receiver latches, thereby reducing dependencies among clock domains. Advantageously, the design of internal logic and asynchronous boundaries of each clock domain, ultimately residing within an IC, can proceed without a priori knowledge of how the clock domain will eventually be used in aggregation with other clock domains.

    摘要翻译： 提供了一种用于同时和/或选择性地自我测试具有多个时钟域的IC的内部逻辑和异步边界的技术。 时钟指令由同时产生的每个时钟域的产品时钟发生器产生; 并且异步接收时钟驱动器基于异步边界的预定周期要求向捕获时钟提供可编程延迟。 异步边界测试要求仅从异步边界接收器锁存器的角度定义，从而减少时钟域之间的依赖关系。 有利地，最终驻留在IC内的每个时钟域的内部逻辑和异步边界的设计可以进行，而无需事先了解时钟域将如何最终用于与其他时钟域的聚合。

    SYSTEM AND PROGRAM PRODUCT FOR FACILITATING FORWARDING OF DATA PACKETS THROUGH A NODE OF A DATA TRANSFER NETWORK USING MULTIPLE TYPES OF FORWARDING TABLES
    9.
    发明申请
    SYSTEM AND PROGRAM PRODUCT FOR FACILITATING FORWARDING OF DATA PACKETS THROUGH A NODE OF A DATA TRANSFER NETWORK USING MULTIPLE TYPES OF FORWARDING TABLES 失效
    系统和程序产品，用于通过使用多种前向表的数据传输网络的节点来转发数据包

    公开(公告)号：US20070248096A1

    公开(公告)日：2007-10-25

    申请号：US11766475

    申请日：2007-06-21

    申请人： Jay Herring ,  Scot Rider

    发明人： Jay Herring ,  Scot Rider

    IPC分类号： H04L12/56

    CPC分类号： H04L45/742 ,  H04L45/00 ,  H04L45/54

    摘要： Method, system and program product are provided for reducing size of memory required for a switching node's forwarding table by employing forwarding tables of different types to map received data packets addressed to downstream nodes and upstream nodes to appropriate output ports of the switching node. The method includes receiving a data packet at a data transfer node of a network and selecting a forwarding table from multiple types of forwarding tables accessible by the node based on an attribute associated with the received data packet, and mapping the data packet to an output port of the node utilizing the forwarding table selected from the multiple types of forwarding tables based on the attribute associated with the packet.

    摘要翻译： 提供方法，系统和程序产品，用于通过采用不同类型的转发表来将接收到的下游节点和上游节点的数据分组映射到交换节点的适当输出端口来减少交换节点的转发表所需的存储器的大小。 该方法包括在网络的数据传输节点处接收数据分组，并且基于与接收到的数据分组相关联的属性，从节点可访问的多种类型的转发表中选择转发表，并将数据分组映射到输出端口 基于与分组关联的属性，利用从多种类型的转发表中选择的转发表来使用该节点。

    METHOD, SYSTEM, AND PROGRAM PRODUCT FOR CONTROLLING TEST DATA OF A LOGIC BUILT-IN SELF-TEST OF AN INTEGRATED CIRCUIT
    10.
    发明申请
    METHOD, SYSTEM, AND PROGRAM PRODUCT FOR CONTROLLING TEST DATA OF A LOGIC BUILT-IN SELF-TEST OF AN INTEGRATED CIRCUIT 失效
    用于控制集成电路逻辑内置自检测试数据的方法，系统和程序产品

    公开(公告)号：US20070240025A1

    公开(公告)日：2007-10-11

    申请号：US11762889

    申请日：2007-06-14

    申请人： Marvin Rich ,  Jay Herring

    发明人： Marvin Rich ,  Jay Herring

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318547

    摘要： A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.

    摘要翻译： 提供了一种利用具有多个锁存器的边界锁存模块来控制测试数据的方法，以便于集成电路（IC）的内部自检的逻辑，其包括提供多个选择装置，用于选择初始化数据以存储在 IC边界锁存模块的多个锁存器。 初始化数据从集成电路的多个扫描路径中选择，并且来自至少一个锁存器的初始化数据被提供作为IC的逻辑电路或IC的输出的输入。 在另一方面，该方法包括从集成电路的外部输入或测试模式发生器中选择一个数据，用于在至少一个锁存器中捕获并输入到多输入签名寄存器，多个输入签名寄存器存储集成电路的签名 由逻辑内置的自检产生。