公开(公告)号：US20060107149A1

公开(公告)日：2006-05-18

申请号：US10980938

申请日：2004-11-04

申请人： Marvin Rich ,  Jay Herring

发明人： Marvin Rich ,  Jay Herring

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.

摘要翻译： 提供了一种利用具有多个锁存器的边界锁存模块来控制测试数据的方法，以便于集成电路（IC）的内部自检的逻辑，其包括提供多个选择装置，用于选择初始化数据以存储在 IC边界锁存模块的多个锁存器。 初始化数据从集成电路的多个扫描路径中选择，并且来自至少一个锁存器的初始化数据被提供作为IC的逻辑电路或IC的输出的输入。 在另一方面，该方法包括从集成电路的外部输入或测试模式发生器中选择一个数据，用于在至少一个锁存器中捕获并输入到多输入签名寄存器，多个输入签名寄存器存储集成电路的签名 由逻辑内置的自检产生。

公开(公告)号：US20050166104A1

公开(公告)日：2005-07-28

申请号：US10753801

申请日：2004-01-08

申请人： Marvin Rich ,  Jay Herring ,  Ronald Linton

发明人： Marvin Rich ,  Jay Herring ,  Ronald Linton

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20

CPC分类号： G01R31/318577 ,  G01R31/31725

摘要： A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock domains. A clock command is generated by an on product clock generator for each clock domain simultaneously; and an asynchronous receive clock driver provides a programmable delay to a capture clock based on predetermined cycle requirements of the asynchronous boundaries. Asynchronous boundary test requirements are defined exclusively from the perspective of the asynchronous boundary receiver latches, thereby reducing dependencies among clock domains. Advantageously, the design of internal logic and asynchronous boundaries of each clock domain, ultimately residing within an IC, can proceed without a priori knowledge of how the clock domain will eventually be used in aggregation with other clock domains.

摘要翻译： 提供了一种用于同时和/或选择性地自我测试具有多个时钟域的IC的内部逻辑和异步边界的技术。 时钟指令由同时产生的每个时钟域的产品时钟发生器产生; 并且异步接收时钟驱动器基于异步边界的预定周期要求向捕获时钟提供可编程延迟。 异步边界测试要求仅从异步边界接收器锁存器的角度定义，从而减少时钟域之间的依赖关系。 有利地，最终驻留在IC内的每个时钟域的内部逻辑和异步边界的设计可以进行，而无需事先了解时钟域将如何最终用于与其他时钟域的聚合。

公开(公告)号：US20070240025A1

公开(公告)日：2007-10-11

申请号：US11762889

申请日：2007-06-14

申请人： Marvin Rich ,  Jay Herring

发明人： Marvin Rich ,  Jay Herring

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.

摘要翻译： 提供了一种利用具有多个锁存器的边界锁存模块来控制测试数据的方法，以便于集成电路（IC）的内部自检的逻辑，其包括提供多个选择装置，用于选择初始化数据以存储在 IC边界锁存模块的多个锁存器。 初始化数据从集成电路的多个扫描路径中选择，并且来自至少一个锁存器的初始化数据被提供作为IC的逻辑电路或IC的输出的输入。 在另一方面，该方法包括从集成电路的外部输入或测试模式发生器中选择一个数据，用于在至少一个锁存器中捕获并输入到多输入签名寄存器，多个输入签名寄存器存储集成电路的签名 由逻辑内置的自检产生。

公开(公告)号：US20050155003A1

公开(公告)日：2005-07-14

申请号：US10753852

申请日：2004-01-08

申请人： Marvin Rich ,  Jay Herring

发明人： Marvin Rich ,  Jay Herring

IPC分类号： G01R31/3185 ,  G06F17/50

CPC分类号： G01R31/318594

摘要： A scalable LBIST control structure provides for testing of multiple independent clock domains within a chip and/or across multiple chips. The LBIST control structure sequences all clock domains through each step of the LBIST sequence synchronously, allowing multiple clock domains and/or multiple chips to be controlled from a common point.

摘要翻译： 可扩展的LBIST控制结构提供了测试芯片内和/或跨多个芯片的多个独立时钟域。 LBIST控制结构通过LBIST序列的每个步骤同步地排列所有时钟域，允许从公共点控制多个时钟域和/或多个芯片。

公开(公告)号：US20060095820A1

公开(公告)日：2006-05-04

申请号：US10981225

申请日：2004-11-04

申请人： Marvin Rich ,  Jay Herring

发明人： Marvin Rich ,  Jay Herring

IPC分类号： G01R31/28

CPC分类号： G01R31/318555 ,  G01R31/318541

摘要： A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being verified is electrically coupled to the tested I/O circuit. A result of verifying of the at least one external signal path is manifested in the integrated circuit's signature, which characterizes a response of the I/O circuit to the LBIST. In another aspect, the verifying of the at least one external signal path includes concurrently testing another I/O circuit of another integrated circuit, which is also electrically coupled to the external signal path.

摘要翻译： 提供了一种测试方法，其包括通过利用逻辑内置自检来测试电子封装环境的集成电路的输入/输出（I / O）电路来验证电子封装环境的至少一个外部信号路径 LBIST），其中被验证的外部信号路径电耦合到所测试的I / O电路。 验证至少一个外部信号路径的结果表现在集成电路的签名中，其表征I / O电路对LBIST的响应。 在另一方面，至少一个外部信号路径的验证包括同时测试另一个也与外部信号路径电耦合的集成电路的I / O电路。

公开(公告)号：US20060242509A1

公开(公告)日：2006-10-26

申请号：US11323449

申请日：2005-12-30

申请人： John Flanagan ,  Jay Herring ,  Tin-Chee Lo

发明人： John Flanagan ,  Jay Herring ,  Tin-Chee Lo

IPC分类号： G01R31/28

CPC分类号： G01R31/31724 ,  G01R31/2891 ,  G01R31/31922

摘要： An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at speed data launch pulse is applied to the first test register in response to said system clock. The data from the first register is input to a logic path in response to applying the at speed data launch pulse to the first test register. An at speed data capture pulse is applied to a second test register in response to the system clock. The output from the logic path is input to the second test register in response to applying the at speed data capture pulse to the second test register. A long data launch pulse is applied to the second test register in response to the system clock. An additional embodiment includes a system for performing AC self-test on an integrated circuit that includes a system clock.

公开(公告)号：US20070253426A1

公开(公告)日：2007-11-01

申请号：US11413526

申请日：2006-04-28

申请人： Jay Herring ,  Aruna Ramanan ,  Craig Stunkel

发明人： Jay Herring ,  Aruna Ramanan ,  Craig Stunkel

IPC分类号： H04L12/56

CPC分类号： H04L12/18 ,  H04L49/1515 ,  H04L49/201 ,  H04L49/25 ,  H04L49/40 ,  H04L49/65

摘要： Efficient, reliable broadcast support is provided to clients of a network built using switching elements that have the capability to replicate packets. Replication patterns are generated and used in broadcasting data in the network. The replication patterns are provided in hardware of the network to enable broadcasting from one node in the network to each node of a broadcast domain of the network.

摘要翻译： 向使用能够复制数据包的交换单元构建的网络的客户端提供高效，可靠的广播支持。 复制模式被生成并用于广播网络中的数据。 在网络的硬件中提供复制模式，以使得能够从网络中的一个节点广播到网络的广播域的每个节点。

公开(公告)号：US20060268725A1

公开(公告)日：2006-11-30

申请号：US11137834

申请日：2005-05-25

申请人： Mark Atkins ,  John Divirgilio ,  Jay Herring ,  John Lewars ,  LeRoy Lundin ,  Nicholas Rash ,  Karen Rash ,  Alison White

发明人： Mark Atkins ,  John Divirgilio ,  Jay Herring ,  John Lewars ,  LeRoy Lundin ,  Nicholas Rash ,  Karen Rash ,  Alison White

IPC分类号： H04L1/00

CPC分类号： H04L43/0817 ,  H04L41/0659

摘要： Network managers are operated in verification mode to facilitate error handling of communications networks. In verification mode, error reporting remains enabled, even for those components of a communications network reporting errors. A step-by-step procedure is provided for handling each type of error that is detected. Subsequent to handling any reported errors, the network manager is removed from verification mode and may be placed in production mode.

摘要翻译： 网络管理员在验证模式下运行，以便于通信网络的错误处理。 在验证模式下，错误报告仍然启用，即使通信网络的组件报告错误。 提供了一个逐步的过程，用于处理检测到的每种类型的错误。 在处理任何报告的错误之后，网络管理器将从验证模式中移除，并可能处于生产模式。

公开(公告)号：US20050149600A1

公开(公告)日：2005-07-07

申请号：US10737989

申请日：2003-12-17

申请人： Jay Herring ,  Scot Rider

发明人： Jay Herring ,  Scot Rider

IPC分类号： H04L12/56 ,  G06F15/16

CPC分类号： H04L45/742 ,  H04L45/00 ,  H04L45/54

摘要： Method, system and program product are provided for reducing size of memory required for a switching node's forwarding table by employing forwarding tables of different types to map received data packets addressed to downstream nodes and upstream nodes to appropriate output ports of the switching node. The method includes receiving a data packet at a data transfer node of a network and selecting a forwarding table from multiple types of forwarding tables accessible by the node based on an attribute associated with the received data packet, and mapping the data packet to an output port of the node utilizing the forwarding table selected from the multiple types of forwarding tables based on the attribute associated with the packet.

摘要翻译： 提供方法，系统和程序产品，用于通过采用不同类型的转发表来将接收到的下游节点和上游节点的数据分组映射到交换节点的适当输出端口来减少交换节点的转发表所需的存储器的大小。 该方法包括在网络的数据传输节点处接收数据分组，并且基于与接收到的数据分组相关联的属性，从节点可访问的多种类型的转发表中选择转发表，并将数据分组映射到输出端口 基于与分组关联的属性，利用从多种类型的转发表中选择的转发表来使用该节点。

公开(公告)号：US20050226145A1

公开(公告)日：2005-10-13

申请号：US10822794

申请日：2004-04-09

申请人： Derrick Garmire ,  Jay Herring ,  Ronald Linton ,  Scot Rider

发明人： Derrick Garmire ,  Jay Herring ,  Ronald Linton ,  Scot Rider

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L49/9063 ,  H04L49/3036 ,  H04L49/3045 ,  H04L49/90 ,  H04L49/9057 ,  H04L49/9078

摘要： Method, system and program product are provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

摘要翻译： 提供方法，系统和程序产品用于数据传输网络的交换节点的分组流控制。 该方法包括基于当前在中央队列中可用的未使用空间的量，主动地管理分配给交换节点的端口的交换节点的中心队列中的空间分配。 在另一方面，该方法包括分别跟踪未分配的空间和空闲的分配空间，其已被用于缓冲由端口接收的分组，但是由于从中央队列中移除分组而进行的先前的管理更新。 每个端口都提供空闲空间，目前分配给该端口和中央队列中当前未分配空间的数量，以分配到端口的一个或多个虚拟通道。